FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 36
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
Lead Free Status / RoHS Status
Not Compliant
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Contents
36
150 APM Register Map ................................................................................................................... 384
151 ACPI and Legacy I/O Register Map ......................................................................................... 385
152 TCO I/O Register Address Map................................................................................................ 403
153 Registers to Control GPIO Address Map.................................................................................. 409
154 IDE Controller PCI Register Address Map (IDE-D31:F1) ......................................................... 415
155 Bus Master IDE I/O Registers .................................................................................................. 430
156 SATA Controller PCI Register Address Map (SATA–D31:F2) ................................................. 433
157 SATA Indexed Registers .......................................................................................................... 452
158 Bus Master IDE I/O Register Address Map .............................................................................. 456
159 UHCI Controller PCI Register Address Map (USB—D29:F0/F1/F2/F3) ................................... 461
160 USB I/O Registers .................................................................................................................... 470
161 Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation ......................... 473
162 USB EHCI PCI Register Address Map (USB EHCI—D29:F7) ................................................. 479
163 Enhanced Host Controller Capability Registers ....................................................................... 496
164 Enhanced Host Controller Operational Register Address Map ................................................ 499
165 Debug Port Register Address Map........................................................................................... 512
166 SMBus Controller PCI Register Address Map (SMBUS—D31:F3) .......................................... 515
167 SMBus I/O Register Address Map............................................................................................ 521
168 AC ‘97 Audio PCI Register Address Map (Audio—D31:F5) ..................................................... 533
169 Intel
170 Native Audio Bus Master Control Registers ............................................................................. 548
171 AC ‘97 Modem PCI Register Address Map (Modem—D31:F6) ............................................... 559
172 Intel
173 Modem Registers ..................................................................................................................... 569
174 Memory-Mapped Registers ...................................................................................................... 579
175 Intel
176 Intel
177 DC Current Characteristics....................................................................................................... 599
178 DC Characteristic Input Signal Association .............................................................................. 600
179 DC Input Characteristics........................................................................................................... 601
180 DC Characteristic Output Signal Association ........................................................................... 603
181 DC Output Characteristics ........................................................................................................ 604
182 Other DC Characteristics.......................................................................................................... 605
183 Clock Timings ........................................................................................................................... 606
184 PCI Interface Timing................................................................................................................. 608
185 IDE PIO and Multiword DMA ModeTiming ............................................................................... 609
186 Ultra ATA Timing (Mode 0, Mode 1, Mode 2) ........................................................................... 610
187 Ultra ATA Timing (Mode 3, Mode 4, Mode 5) ........................................................................... 612
188 Universal Serial Bus Timing ..................................................................................................... 614
189 SATA Interface Timings............................................................................................................ 615
190 SMBus Timing .......................................................................................................................... 615
192 LPC Timing............................................................................................................................... 616
193 Miscellaneous Timings ............................................................................................................. 616
191 AC’97 Timing ............................................................................................................................ 616
194 Power Sequencing and Reset Signal Timings ......................................................................... 617
195 Power Management Timings .................................................................................................... 618
196 Test Mode Selection................................................................................................................. 631
197 XOR Test Pattern Example ...................................................................................................... 632
198 XOR Chain #1 (RTCRST# Asserted for 4 PCI Clocks While PWROK Active) ......................... 633
199 XOR Chain #2 (RTCRST# Asserted for 5 PCI Clocks While PWROK Active) ......................... 634
®
®
®
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ICH5 Modem Mixer Register Configuration .................................................................... 568
ICH5 Ballout by Signal Name ......................................................................................... 590
ICH5 Ballout by Ball Number .......................................................................................... 594
ICH5 Audio Mixer Register Configuration...................................................................... 546
Intel
®
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