FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 648
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
Lead Free Status / RoHS Status
Not Compliant
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Register Index
648
Table 204. Intel
Base Class Code
SMB Base Address
Register
Interrupt Line
Interrupt Pin
Host Configuration
Vendor Identification
Device Identification
PCI Command
PCI Device Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Header Type
Native Audio Mixer Base
Address
Native Audio Bus Mastering
Base Address
Mixer Base Address(Mem)
Bus Master Base
Address(Mem)
Subsystem Vendor ID
Subsystem ID
Capabilities Pointer
Interrupt Line
Interrupt Pin
Programmable Codec ID
®
Register Name
ICH5 PCI Configuration Registers (Sheet 10 of 11)
2Ch – 2Dh
2Eh – 2Fh
00h – 01h
02h – 03h
04h – 05h
10h – 13h
14h – 17h
06h – 07h
20 – 23h
18 – 1Bh
Offset
1C – 1F
0Bh
3Ch
3Dh
0Ah
0Bh
0Eh
3Ch
3Dh
40h
08h
09h
34h
40h
AC’97 Audio Controller (D31:F5)
Section 14.1.8, “SMB_BASE—SMBUS Base Address Register
(SMBUS—D31:F3)” on page 518
Section 14.1.8, “SMB_BASE—SMBUS Base Address Register
(SMBUS—D31:F3)” on page 518
Section 14.1.11, “INT_LN—Interrupt Line Register (SMBUS—
D31:F3)” on page 519
Section 14.1.12, “INT_PN—Interrupt Pin Register (SMBUS—
D31:F3)” on page 519
Section 14.1.13, “HOSTC—Host Configuration Register
(SMBUS—D31:F3)” on page 520
Section 15.1.1, “VID—Vendor Identification Register (Audio—
D31:F5)” on page 534
Section 15.1.2, “DID—Device Identification Register (Audio—
D31:F5)” on page 534
Section 15.1.3, “PCICMD—PCI Command Register (Audio—
D31:F5)” on page 535
Section 15.1.4, “PCISTS—PCI Status Register (Audio—
D31:F5)” on page 536
Section 15.1.5, “RID—Revision Identification Register (Audio—
D31:F5)” on page 537
Section 15.1.6, “PI—Programming Interface Register (Audio—
D31:F5)” on page 537
Section 15.1.7, “SCC—Sub Class Code Register (Audio—
D31:F5)” on page 537
Section 15.1.8, “BCC—Base Class Code Register (Audio—
D31:F5)” on page 537
Section 15.1.9, “HEADTYP—Header Type Register (Audio—
D31:F5)” on page 538
Section 15.1.10, “NAMBAR—Native Audio Mixer Base Address
Register (Audio—D31:F5)” on page 538
Section 15.1.10, “NAMBAR—Native Audio Mixer Base Address
Register (Audio—D31:F5)” on page 538
Section 15.1.12, “MMBAR—Mixer Base Address Register
(Audio—D31:F5)” on page 539
Section 15.1.13, “MBBAR—Bus Master Base Address Register
(Audio—D31:F5)” on page 540
Section 15.1.14, “SVID—Subsystem Vendor Identification
Register (Audio—D31:F5)” on page 540
Section 15.1.15, “SID—Subsystem Identification Register
(Audio—D31:F5)” on page 541
Section 15.1.16, “CAP_PTR—Capabilities Pointer Register
(Audio—D31:F5)” on page 541
Section 15.1.17, “INT_LN—Interrupt Line Register (Audio—
D31:F5)” on page 541
Section 15.1.18, “INT_PN—Interrupt Pin Register (Audio—
D31:F5)” on page 542
Section 15.1.19, “PCID—Programmable Codec Identification
Register (Audio—D31:F5)” on page 542
Intel
®
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