XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 103

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Maximum Bitstream Size for Daisy-Chains
The maximum bitstream length supported by Spartan-3E
FPGAs in serial daisy-chains is 4,294,967,264 bits
(4 Gbits), roughly equivalent to a daisy-chain with 720
XC3S1600E FPGAs. This is a limit only for serial
daisy-chains where configuration data is passed via the
FPGA’s DOUT pin. There is no such limit for JTAG chains.
Configuration Sequence
For additional information including I/O behavior before and
during configuration, refer to the “Sequence of Events”
chapter in UG332.
The Spartan-3E configuration process is three-stage pro-
cess that begins after the FPGA powers on (a POR event)
or after the PROG_B input is asserted. Power-On Reset
(POR) occurs after the V
2 supplies reach their respective input threshold levels.
After either a POR or PROG_B event, the three-stage con-
figuration process begins.
1. The FPGA clears (initializes) the internal configuration
2. Configuration data is loaded into the internal memory.
3. The user-application is activated by a start-up process.
Figure 66
configuration logic, showing the interaction of different
device inputs and Bitstream Generator (BitGen) options. A
DS312-2 (v3.8) August 26, 2009
Product Specification
memory.
is a generalized block diagram of the Spartan-3E
R
CCINT
, V
CCAUX
, and the V
CCO
www.xilinx.com
Bank
flow diagram for the configuration sequence of the Serial
and Parallel modes appears in
the Boundary-Scan or JTAG configuration sequence.
Initialization
Configuration automatically begins after power-on or after
asserting the FPGA PROG_B pin, unless delayed using the
FPGA’s INIT_B pin. The FPGA holds the open-drain INIT_B
signal Low while it clears its internal configuration memory.
Externally holding the INIT_B pin Low forces the configura-
tion sequencer to wait until INIT_B again goes High.
The FPGA signals when the memory-clearing phase is
complete by releasing the open-drain INIT_B pin, allowing
the pin to go High via the external pull-up resistor to
VCCO_2.
Loading Configuration Data
After initialization, configuration data is written to the
FPGA’s internal memory. The FPGA holds the Global
Set/Reset (GSR) signal active throughout configuration,
holding all FPGA flip-flops in a reset state. The FPGA sig-
nals when the entire configuration process completes by
releasing the DONE pin, allowing it to go High.
The FPGA configuration sequence can also be initiated by
asserting PROG_B. Once released, the FPGA begins
clearing its internal configuration memory, and progresses
through the remainder of the configuration process.
Figure
Functional Description
67.
Figure 68
shows
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