XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 82

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Functional Description
If the FPGA's V
valid, then the FPGA waits for VCCO_2 to reach its mini-
mum threshold voltage before starting configuration. This
threshold voltage is labeled as V
ule 3 and ranges from approximately 0.4V to 1.0V, substan-
tially lower than the SPI Flash PROM's minimum voltage.
Once all three FPGA supplies reach their respective Power
On Reset (POR) thresholds, the FPGA starts the configura-
tion process and begins initializing its internal configuration
memory. Initialization requires approximately 1 ms (T
minimum in
de-asserts INIT_B, selects the SPI Flash PROM, and starts
sending the appropriate read command. The SPI Flash
PROM must be ready for read operations at this time. Spar-
tan-3E FPGAs issue the read command just once. If the SPI
Flash is not ready, then the FPGA does not properly config-
ure.
If the 3.3V supply is last in the sequence and does not ramp
fast enough, or if the SPI Flash PROM cannot be ready
when required by the FPGA, delay the FPGA configuration
process by holding either the FPGA's PROG_B input or
INIT_B input Low, as highlighted in
FPGA when the SPI Flash PROM is ready. For example, a
simple R-C delay circuit attached to the INIT_B pin forces
the FPGA to wait for a preselected amount of time. Alter-
nately, a Power Good signal from the 3.3V supply or a sys-
tem reset signal accomplishes the same purpose. Use an
open-drain or open-collector output when driving PROG_B
or INIT_B.
SPI Flash PROM Density Requirements
Table 57
program a single Spartan-3E FPGA. Commercially avail-
able SPI Flash PROMs range in density from 1 Mbit to 128
Mbits. A multiple-FPGA daisy-chained application requires
a SPI Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-den-
sity SPI Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the SPI Flash
PROM can also store application code for a MicroBlaze™
82
Figure 55: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
shows the smallest usable SPI Flash PROM to
Table 111
CCINT
FPGA VCCO_2 minimum
Power On Reset Voltage
of Module 3, after which the FPGA
and V
(V
SPI Flash PROM
minimum voltage
CCINT
already valid)
CCAUX
CCO2T
, V
(V
CCAUX
Figure
CCO2T
3.3V Supply
supplies are already
in
)
Table 74
54. Release the
SPI Flash cannot be selected
FPGA initializes configuration
of Mod-
www.xilinx.com
POR
memory
,
PROM CS
delay
SPI Flash
RISC processor core integrated in the Spartan-3E FPGA.
See
Table 57: Number of Bits to Program a Spartan-3E
FPGA and Smallest SPI Flash PROM
CCLK Frequency
In SPI Flash mode, the FPGA’s internal oscillator generates
the configuration clock frequency. The FPGA provides this
clock on its CCLK output pin, driving the PROM’s clock input
pin. The FPGA starts configuration at its lowest frequency
and increases its frequency for the remainder of the config-
uration process if so specified in the configuration bitstream.
The maximum frequency is specified using the
bitstream generator option. The maximum frequency sup-
ported by the FPGA configuration logic depends on the tim-
ing for the SPI Flash device. Without examining the timing
for a specific SPI Flash PROM, use ConfigRate = 12 or
lower. SPI Flash PROMs that support the FAST READ com-
mand support higher data rates. Some such PROMs sup-
port up to ConfigRate = 25 and beyond but require careful
data sheet analysis. See
Configuration Timing
Using the SPI Flash Interface after Configuration
After the FPGA successfully completes configuration, all of
the pins connected to the SPI Flash PROM are available as
user-I/O pins.
(T
XC3S1200E
XC3S1600E
POR
XC3S100E
XC3S250E
XC3S500E
(t
Using the SPI Flash Interface after
Device
Time
)
VSL
)
SPI Flash available for
read operations
SPI Flash PROM
FPGA accesses
access, otherwise delay
SPI Flash PROM must
FPGA configuration
be ready for FPGA
Configuration
Number of
1,353,728
2,270,208
3,841,184
5,969,696
581,344
for more detailed timing analysis.
Bits
Serial Peripheral Interface (SPI)
DS312-2_50b_110206
DS312-2 (v3.8) August 26, 2009
Product Specification
SPI Flash PROM
Smallest Usable
Configuration.
1 Mbit
2 Mbit
4 Mbit
4 Mbit
8 Mbit
ConfigRate
R