XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 169

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

VQ100: 100-lead Very-thin Quad Flat Package
The XC3S100E, XC3S250E, and the XC3S500E devices
are available in the 100-lead very-thin quad flat package,
VQ100. All devices share a common footprint for this pack-
age as shown in
Table 131
bank number and then by pin name. Pins that form a differ-
ential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
The VQ100 package does not support the Byte-wide
Peripheral Interface (BPI) configuration mode. Conse-
quently, the VQ100 footprint has fewer DUAL-type pins than
other packages.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at:
http://www.xilinx.com/support/documentation/data_sheets/s3e_pin.zip
Pinout Table
Table 131
FPGAs in the VQ100 package.
Table 131: VQ100 Package Pinout
DS312-4 (v3.8) August 26, 2009
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
lists all the package pins. They are sorted by
IO
IO_L01N_0
IO_L01P_0
IO_L02N_0/GCLK5
IO_L02P_0/GCLK4
IO_L03N_0/GCLK7
IO_L03P_0/GCLK6
IO_L05N_0/GCLK11
IO_L05P_0/GCLK10
IO_L06N_0/VREF_0
IO_L06P_0
IO_L07N_0/HSWAP
IO_L07P_0
IP_L04N_0/GCLK9
IP_L04P_0/GCLK8
VCCO_0
VCCO_0
IO_L01N_1
IO_L01P_1
IO_L02N_1
IO_L02P_1
shows the pinout for production Spartan-3E
R
Table 131
XC3S100E
XC3S250E
XC3S500E
Pin Name
and
Figure
Number
VQ100
81.
P92
P79
P78
P84
P83
P86
P85
P91
P90
P95
P94
P99
P98
P89
P88
P82
P97
P54
P53
P58
P57
Pin
VCCO
VCCO
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
DUAL
GCLK
GCLK
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 131: VQ100 Package Pinout (Continued)
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
IO_L03N_1/RHCLK1
IO_L03P_1/RHCLK0
IO_L04N_1/RHCLK3
IO_L04P_1/RHCLK2
IO_L05N_1/RHCLK5
IO_L05P_1/RHCLK4
IO_L06N_1/RHCLK7
IO_L06P_1/RHCLK6
IO_L07N_1
IO_L07P_1
IP/VREF_1
VCCO_1
VCCO_1
IO/D5
IO/M1
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L03N_2/D6/GCLK13
IO_L03P_2/D7/GCLK12
IO_L04N_2/D3/GCLK15
IO_L04P_2/D4/GCLK14
IO_L06N_2/D1/GCLK3
IO_L06P_2/D2/GCLK2
IO_L07N_2/DIN/D0
IO_L07P_2/M0
IO_L08N_2/VS1
IO_L08P_2/VS2
IO_L09N_2/CCLK
IO_L09P_2/VS0
IP/VREF_2
IP_L05N_2/M2/GCLK1
IP_L05P_2/RDWR_B/
GCLK0
VCCO_2
VCCO_2
IO_L01N_3
IO_L01P_3
XC3S100E
XC3S250E
XC3S500E
Pin Name
Number
Pinout Descriptions
VQ100
P61
P60
P63
P62
P66
P65
P68
P67
P71
P70
P69
P55
P73
P34
P42
P25
P24
P27
P26
P33
P32
P36
P35
P41
P40
P44
P43
P48
P47
P50
P49
P30
P39
P38
P31
P45
Pin
P3
P2
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
VCCO
VCCO
VCCO
VCCO
VREF
VREF
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
Type
I/O
I/O
I/O
I/O
169