XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 143

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital Fre-
quency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applica-
tions. All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
tables
that only employs the DLL component. When the DFS
and/or the PS components are used together with the DLL,
then the specifications listed in the DFS and PS tables
(Table 106
ing ones in the DLL tables. DLL specifications that do not
change with the addition of DFS or PS functions are pre-
sented in
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Delay-Locked Loop (DLL)
Table 104: Recommended Operating Conditions for the DLL
Notes:
1.
2.
3.
4.
DS312-3 (v3.8) August 26, 2009
Product Specification
Input Frequency Ranges
F
Input Pulse Requirements
CLKIN_PULSE
Input Clock Jitter Tolerance and Delay Path Variation
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL
CLKFB_DELAY_VAR_EXT
CLKIN
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
(Table 104
CLKIN_FREQ_DLL
Table 104
Symbol
through
R
and
Table
and
Table
Table
109) supersede any correspond-
105) apply to any application
Frequency of the CLKIN
clock input
CLKIN pulse width as a
percentage of the CLKIN
period
Cycle-to-cycle jitter at the
CLKIN input
Allowable variation of off-chip feedback delay from the DCM
output to the CLKFB input
Period jitter at the CLKIN input
105.
Description
(4)
www.xilinx.com
Stepping 0
Stepping 1
F
F
F
F
CLKIN
CLKIN
CLKIN
CLKIN
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a histo-
gram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock peri-
ods sampled. In a histogram of cycle-cycle jitter, the mean
value is zero.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the fre-
quency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469,
Spread-Spectrum Clocking Reception for Displays
for details.
< 150 MHz
> 150 MHz
< 150 MHz
> 150 MHz
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
All
(3)
Table
40%
45%
DC and Switching Characteristics
Min
N/A
5
(2)
-
-
-
-
106.
-5
275
Speed Grade
±300
±150
Max
60%
55%
N/A
±1
±1
(3)
40%
45%
Min
5
(2)
-
-
-
-
-4
200
240
±300
±150
90
Max
60%
55%
±1
±1
(3)
(3)
(3)
Units
MHz
MHz
MHz
ps
ps
ns
ns
-
-
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