XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 12

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Functional Description
Input Delay Functions
Each IOB has a programmable delay block that optionally
delays the input signal. In
coarse delay element that can be bypassed. The input sig-
nal then feeds a 6-tap delay line. The coarse and tap delays
vary; refer to timing reports for specific delay values. All six
taps are available via a multiplexer for use as an asynchro-
nous input directly into the FPGA fabric. In this way, the
delay is programmable in 12 steps. Three of the six taps are
also available via a multiplexer to the D inputs of the syn-
chronous storage elements. The delay inserted in the path
to the storage element can be varied in six steps. The first,
coarse delay element is common to both asynchronous and
synchronous paths, and must be either used or not used for
both paths.
The delay values are set up in the silicon once at configura-
tion time—they are non-modifiable in device operation.
The primary use for the input delay element is to adjust the
input delay path to ensure that there is no hold time require-
ment when using the input flip-flop(s) with a global clock.
The default value is chosen automatically by the Xilinx soft-
ware tools as the value depends on device size and the spe-
cific device edge where the flip-flop resides. The value set
by the Xilinx ISE software is indicated in the Map report
12
PAD
Figure
Figure 6: Programmable Fixed Input Delay Elements
6, the signal path has a
Coarse Delay
www.xilinx.com
generated by the implementation tools, and the resulting
effects on input timing are reported using the Timing Ana-
lyzer tool.
If the design uses a DCM in the clock path, then the delay
element can be safely set to zero because the
Delay-Locked Loop (DLL)
ensures that there is still no input hold time requirement.
Both asynchronous and synchronous values can be modi-
fied, which is useful where extra delay is required on clock
or data inputs, for example, in interfaces to various types of
RAM.
These
IBUF_DELAY_VALUE and the IFD_DELAY_VALUE param-
eters. The default IBUF_DELAY_VALUE is 0, bypassing the
delay elements for the asynchronous input. The user can
set this parameter to 0-12. The default IFD_DELAY_VALUE
is AUTO. IBUF_DELAY_VALUE and IFD_DELAY_VALUE
are independent for each input. If the same input pin uses
both registered and non-registered input paths, both param-
eters can be used, but they must both be in the same half of
the total delay (both either bypassing or using the coarse
delay element).
Asynchronous input (I)
IBUF_DELAY_VALUE
delay
Synchronous input (IQ1)
Synchronous input (IQ2)
IFD_DELAY_VALUE
values
D Q
D Q
UG331_c10_09_011508
are
DS312-2 (v3.8) August 26, 2009
compensation automatically
defined
Product Specification
through
the
R