XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 109

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Bitstream Generator (BitGen) Options
For additional information, refer to the “Configuration Bit-
stream Generator (BitGen) Settings” chapter in UG332.
Various Spartan-3E FPGA functions are controlled by spe-
cific bits in the configuration bitstream image. These values
Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options
DS312-2 (v3.8) August 26, 2009
Product Specification
ConfigRate
StartupClk
UnusedPin
DONE_cycle
GWE_cycle
GTS_cycle
LCK_cycle
Option Name
R
Pins/Function
Configuration,
shift registers,
Configuration
Configuration
Configuration
Configuration
Configuration
All flip-flops,
Block RAM,
LUT RAMs,
All I/O pins,
Unused I/O
and SRL16
DONE pin,
Affected
Startup
Startup
Startup
Startup
DCMs,
CCLK,
Pins
12, 25, 50
Pulldown
1, 2, 3, 4,
1, 2, 3, 4,
1, 2, 3, 4,
0, 1, 2, 3,
(default)
Pullnone
UserClk
NoWait
Values
1, 3, 6,
Pullup
4, 5, 6
Done
Keep
Done
Keep
Cclk
Jtag
5, 6
5, 6
5, 6
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest
frequency, and the new setting is loaded as part of the configuration bitstream. The
software default value is 1 (~1.5 MHz) starting with ISE 8.1, Service Pack 1.
Default. The CCLK signal (internally or externally generated) controls the startup
sequence when the FPGA transitions from configuration mode to the user mode. See
Start-Up.
A clock signal from within the FPGA application controls the startup sequence when
the FPGA transitions from configuration mode to the user mode. See Start-Up. The
FPGA application supplies the user clock on the CLK pin on the
STARTUP_SPARTAN3E primitive.
The JTAG TCK input controls the startup sequence when the FPGA transitions from
the configuration mode to the user mode. See Start-Up.
Default. All unused I/O pins and input-only pins have a pull-down resistor to GND.
All unused I/O pins and input-only pins have a pull-up resistor to the VCCO_# supply
for its associated I/O bank.
All unused I/O pins and input-only pins are left floating (Hi-Z, high-impedance,
three-state). Use external pull-up or pull-down resistors or logic to apply a valid signal
level.
Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See
Start-Up.
Selects the Configuration Startup phase that asserts the internal write-enable signal to
all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read
and write operations. See Start-Up.
Waits for the DONE pin input to go High before asserting the internal write-enable
signal to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and
write operations are enabled at this time.
Retains the current GWE_cycle setting for partial reconfiguration applications.
Selects the Configuration Startup phase that releases the internal three-state control,
holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point. See Start-Up.
Waits for the DONE pin input to go High before releasing the internal three-state
control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive,
if so configured, after this point.
Retains the current GTS_cycle setting for partial reconfiguration applications.
The FPGA does not wait for selected DCMs to lock before completing configuration.
If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE,
the FPGA waits for such DCMs to acquire their respective input clock and assert their
LOCKED output. This setting selects the Configuration Startup phase where the FPGA
waits for the DCMs to lock.
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are specified when creating the bitstream image with the
Bitstream Generator (BitGen) software.
Table 69
FPGAs.
provides a list of all BitGen options for Spartan-3E
Description
Functional Description
109