XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 68

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Functional Description
Configuration Bitstream Image Sizes
A specific Spartan-3E part type always requires a constant
number of configuration bits, regardless of design complex-
ity, as shown in
multiple-FPGA daisy-chain design roughly equals the sum
of the individual file sizes.
Table 45: Number of Bits to Program a Spartan-3E
FPGA (Uncompressed Bitstreams)
Pin Behavior During Configuration
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
Table 46: Pin Behavior during Configuration
68
IP* (input-only)
IO* (user-I/O)
DOUT/BUSY
MOSI/CSI_B
Spartan-3E FPGA
Pin Name
PROG_B
HSWAP
CSO_B
INIT_B
DONE
CCLK
XC3S1200E
XC3S1600E
TMS
TDO
TCK
TDI
XC3S100E
XC3S250E
XC3S500E
M2
M1
M0
D7
D6
D5
D4
D3
D2
Table
Master Serial
CCLK (I/O)
PROG_B
HSWAP
45. The configuration file size for a
INIT_B
DONE
DOUT
TMS
TDO
TCK
TDI
0
0
0
Configuration Bits
SPI (Serial
CCLK (I/O)
PROG_B
Number of
HSWAP
CSO_B
1,353,728
2,270,208
3,841,184
5,969,696
INIT_B
Flash)
DONE
DOUT
MOSI
581,344
TMS
TDO
TCK
TDI
0
0
1
BPI (Parallel
NOR Flash)
CCLK (I/O)
PROG_B
1 = Down
HSWAP
CSO_B
INIT_B
DONE
0 = Up
CSI_B
BUSY
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TMS
TDO
TCK
TDI
D7
D6
D5
D4
D3
D2
0
1
Table 46
configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and
the HSWAP pin. The mode select pins determine which of
the I/O pins are borrowed during configuration and how they
function. In JTAG configuration mode, no user-I/O pins are
borrowed for configuration.
All user-I/O pins, input-only pins, and dual-purpose pins that
are not actively involved in the currently-select configuration
mode are high impedance (floating, three-stated, Hi-Z) dur-
ing the configuration process. These pins are indicated in
Table 46
The HSWAP input controls whether all user-I/O pins,
input-only pins, and dual-purpose pins have a pull-up resis-
tor to the supply rail or not. When HSWAP is Low, each pin
has an internal pull-up resistor that is active throughout con-
figuration. After configuration, pull-up and pull-down resis-
tors are available in the FPGA application as described in
Pull-Up and Pull-Down
The yellow-shaded table entries or cells represent pins
where the pull-up resistor is always enabled during configu-
ration, regardless of the HSWAP input. The post-configura-
tion behavior of these pins is defined by Bitstream
Generator options as defined in
PROG_B
HSWAP
DONE
JTAG
TMS
TDO
TCK
TDI
1
0
1
as gray shaded table entries or cells.
shows how various pins behave during the FPGA
PROG_B
CCLK (I)
Parallel
HSWAP
CSO_B
INIT_B
DONE
CSI_B
BUSY
Slave
TMS
TDO
TCK
TDI
D7
D6
D5
D4
D3
D2
1
1
0
Resistors.
DS312-2 (v3.8) August 26, 2009
Slave Serial
Table
PROG_B
CCLK (I)
HSWAP
INIT_B
DONE
DOUT
TMS
TCK
TDO
TDI
1
1
1
69.
Product Specification
I/O Bank
V
V
V
V
V
V
CCAUX
CCAUX
CCAUX
CCAUX
CCAUX
CCAUX
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
(3)
R