EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 121

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: I/O Features in Cyclone IV Devices
Termination Scheme for I/O Standards
Table 6–3. Cyclone IV Devices Supported I/O Standards and Constraints (Part 2 of 2)
Termination Scheme for I/O Standards
© December 2010 Altera Corporation
PPDS
LVDS
RSDS and
mini-LVDS
BLVDS
LVPECL
Notes to
(1) Cyclone IV GX devices only support right I/O pins.
(2) The PCI-clamp diode must be enabled for 3.3-V/3.0-V LVTTL/LVCMOS.
(3) The Cyclone IV architecture supports the MultiVolt I/O interface feature that allows Cyclone IV devices in all packages to interface with I/O systems
(4) Cyclone IV GX devices do not support 1.2-V V
(5) Differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed as inverted. Differential HSTL and SSTL
(6) PPDS, mini-LVDS, and RSDS are only supported on output pins.
(7) LVPECL is only supported on clock inputs.
(8) Bus LVDS (BLVDS) output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses LVDS input buffer.
(9) 1.2-V HSTL input is supported at both column and row I/Os regardless of Class I or Class II.
(10) True LVDS, RSDS, and mini-LVDS I/O standards are supported in right I/O pins, while emulated LVDS, RSDS, and mini-LVDS I/O standards are
I/O Standard
that have different supply voltages.
GPIO pins. Configuration scheme is not support at 1.2 V, therefore bank 9 can not be powered up at 1.2-V V
inputs treat differential inputs as two single-ended HSTL and SSTL inputs and only decode one of them. Differential HSTL and SSTL are only
supported on CLK pins.
supported in the top, bottom, and right I/O pins.
(10)
(6)
(8)
Table
(7)
(6)
f
6–3:
Differential
Differential
Differential
Differential
Differential
Cyclone IV devices support PCI and PCI-X I/O standards at 3.0-V V
PCI and PCI-X I/O are fully compatible for direct interfacing with 3.3-V PCI systems
without requiring any additional components. The 3.0-V PCI and PCI-X outputs meet
the V
margin.
For more information about the 3.3/3.0/2.5-V LVTTL & LVCMOS multivolt I/O
support, refer to
LVTTL/LVCMOS I/O
This section describes recommended termination schemes for voltage-referenced and
differential I/O standards.
The 3.3-V LVTTL, 3.0-V LVTTL and LVCMOS, 2.5-V LVTTL and LVCMOS, 1.8-V
LVTTL and LVCMOS, 1.5-V LVCMOS, 1.2-V LVCMOS, 3.0-V PCI, and PCI-X
I/O standards do not specify a recommended termination scheme per the JEDEC
standard
Type
IH
and V
IL
ANSI/TIA/
Standard
requirements of 3.3-V PCI and PCI-X inputs with sufficient noise
Support
EIA-644
AN 447: Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5-V
CCIO
—
—
—
—
in banks 3 and 9. I/O pins in bank 9 are dual-purpose I/O pins that are used as configuration or
Systems.
Input
2.5
2.5
2.5
V
—
—
CCIO
Level (in V)
Output
2.5
2.5
2.5
2.5
—
CLK,
DQS
—
v
—
—
v
Column I/O Pins
PLL_OUT
Cyclone IV Device Handbook, Volume 1
v
v
v
—
—
CCIO
.
User
Pins
I/O
v
v
v
v
CCIO
—
. The 3.0-V
Row I/O
CLK,
DQS
v
v
—
—
—
User I/O
Pins(1)
6–13
Pins
v
v
v
v
—