EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 99
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EP4CE40F29C8N
Manufacturer Part Number
EP4CE40F29C8N
Description
IC CYCLONE IV FPGA 40K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE40F29C8N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1134000
Number Of I /o
532
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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EP4CE40F29C8N
Manufacturer:
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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
Figure 5–23. PLL Reconfiguration Scan Chain
© December 2010 Altera Corporation
configupdate
scandataout
scanclkena
scandone
scandata
scanclk
areset
1
D0_old
Figure 5–23
When reconfiguring the counter clock frequency, the corresponding counter phase
shift settings cannot be reconfigured using the same interface. You can reconfigure
phase shifts in real time using the dynamic phase shift reconfiguration interface. If
you reconfigure the counter frequency, but wish to keep the same non-zero phase shift
setting (for example, 90°) on the clock output, you must reconfigure the phase shift
after reconfiguring the counter clock frequency.
Post-Scale Counters (C0 to C4)
You can configure multiply or divide values and duty cycle of post-scale counters in
real time. Each counter has an 8-bit high time setting and an 8-bit low time setting.
The duty cycle is the ratio of output high or low time to the total cycle time, that is the
sum of the two. Additionally, these counters have two control bits, rbypass, for
bypassing the counter, and rselodd, to select the output clock duty cycle.
When the rbypass bit is set to 1, it bypasses the counter, resulting in a divide by one.
When this bit is set to 0, the PLL computes the effective division of the VCO output
frequency based on the high and low time counters. For example, if the post-scale
divide factor is 10, the high and low count values are set to 5 and 5, to achieve a
50–50% duty cycle. The PLL implements this duty cycle by transitioning the output
clock from high-to-low on the rising edge of the VCO output clock. However, a 4 and
6 setting for the high and low count values, respectively, would produce an output
clock with a 40–60% duty cycle.
D0 (LSB)
shows a functional simulation of the PLL reconfiguration feature.
Dn (MSB)
Dn_old
Cyclone IV Device Handbook, Volume 1
Dn
5–37
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