EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 378

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–12
Figure 2–7. Sample Reset Sequence of Receiver Only Channel—Receiver CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
(3) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
Cyclone IV Device Handbook, Volume 2
Output Status Signals
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
CDR Control Signals
LTR_LTD_Manual
LTD_Manual
Figure
Reset Signals
rx_analogreset
rx_locktorefclk
rx_digitalreset
rx_locktodata
2–7:
busy (3)
duration, refer to the
duration, refer to the
Receiver Only Channel—Receiver CDR in Manual Lock Mode
This configuration contains only a receiver channel. If you create a Receiver Only
instance in the ALTGX MegaWizard Plug-In Manager with receiver CDR in manual
lock mode, use the reset sequence shown in
As shown in
in manual lock mode:
1. After power up, wait for the busy signal to be asserted.
2. Keep the rx_digitalreset and rx_locktorefclk signals asserted and the
3. After deassertion of the busy signal, wait for two parallel clock cycles to deassert
4. Wait for at least t
5. Deassert rx_digitalreset at least t
rx_locktodata signal deasserted during this time period.
the rx_analogreset signal.
same time, assert the rx_locktodata signal (marker 3).
after asserting the rx_locktodata signal. At this point, the receiver is ready to
receive data.
Cyclone IV Device Datasheet
Cyclone IV Device Datasheet
Figure
Two parallel clock cycles
1
2–7, perform the following reset procedure for the receiver CDR
LTR_LTD_Manual
2
chapter.
, then deassert the rx_locktorefclk signal. At the
t
LTR_LTD_Manual
chapter.
(1)
LTD_Manual
Figure
Chapter 2: Cyclone IV Reset Control and Power Down
t
3
3
LTD_Manual
(the time between markers 3 and 4)
2–7.
(2)
4
© December 2010 Altera Corporation
Transceiver Reset Sequences