EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 294
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4CE40F29C8N
Manufacturer Part Number
EP4CE40F29C8N
Description
IC CYCLONE IV FPGA 40K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE40F29C8N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1134000
Number Of I /o
532
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE40F29C8N
Manufacturer:
ALTERA43
Quantity:
1 602
Part Number:
EP4CE40F29C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4CGX15BN11C8N PDF datasheet
- EP4CGX15BN11C8N PDF datasheet #2
- EP4CGX15BN11C8N PDF datasheet #3
- EP4CGX15BN11C8N PDF datasheet #4
- Current page: 294 of 478
- Download datasheet (13Mb)
1–14
Deserializer
Cyclone IV Device Handbook, Volume 2
f
1
■
Actual lock time depends on the transition density of the incoming data and the PPM
difference between the receiver input reference clock and the upstream transmitter
reference clock.
Transition from the LTD state to the LTR state occurs when either of the following
conditions is met:
■
■
In automatic lock mode, the switch from LTR to LTD states is indicated by the
assertion of the rx_freqlocked signal and the switch from LTD to LTR states
indicated by the de-assertion of the rx_freqlocked signal.
Manual Lock Mode
State transitions are controlled manually by using rx_locktorefclk and
rx_locktodata ports. The LTR/LTD controller sets the CDR state depending on the
logic level on the rx_locktorefclk and rx_locktodata ports. This mode
provides the flexibility to control the CDR for a reduced lock time compared to the
automatic lock mode. In automatic lock mode, the LTR/LTD controller relies on the
PPM detector and the phase relationship detector to set the CDR in LTR or LTD mode.
The PPM detector and phase relationship detector reaction times can be too long for
some applications that require faster CDR lock time.
In manual lock mode, the rx_freqlocked signal is asserted when the CDR is in LTD
state and de-asserted when CDR is in LTR state. For descriptions of
rx_locktorefclk and rx_locktodata port controls, refer to
page
If you do not enable the optional rx_locktorefclk and rx_locktodata ports,
the Quartus II software automatically configures the LTR/LTD controller in automatic
lock mode.
The recommended transceiver reset sequence varies depending on the CDR lock
mode. For more information about the reset sequence recommendations, refer to the
Reset Control and Power Down for Cyclone IV GX Devices
The deserializer converts received serial data from the receiver input buffer to parallel
8- or 10-bit data. Serial data is assumed to be received from the LSB to the MSB. The
deserializer operates with the high-speed recovered clock from the CDR with the
frequency at half of the serial data rate.
The recovered clock is within the configured part per million (PPM) frequency
threshold setting with respect to the CDR clocks from multipurpose PLL.
Signal detection circuitry indicates the absence of valid signal levels at the receiver
input buffer. This condition is valid for PCI Express (PIPE) mode only. CDR
transitions are not dependent on signal detection circuitry in other modes.
The recovered clock is not within the configured PPM frequency threshold setting
with respect to CDR clocks from multipurpose PLLs.
1–80.
Chapter 1: Cyclone IV Transceivers Architecture
chapter.
© December 2010 Altera Corporation
Table 1–27 on
Receiver Channel Datapath
Related parts for EP4CE40F29C8N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: