EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 84
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EP4CE40F29C8N
Manufacturer Part Number
EP4CE40F29C8N
Description
IC CYCLONE IV FPGA 40K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE40F29C8N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1134000
Number Of I /o
532
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE40F29C8N
Manufacturer:
ALTERA43
Quantity:
1 602
Part Number:
EP4CE40F29C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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5–22
Clock Feedback Modes
Source-Synchronous Mode
Cyclone IV Device Handbook, Volume 1
1
1
Cyclone IV PLLs support up to five different clock feedback modes. Each mode
allows clock multiplication and division, phase shifting, and programmable duty
cycle. For the supported feedback modes, refer to
Cyclone IV GX PLLs and
Input and output delays are fully compensated by the PLL only if you are using the
dedicated clock input pins associated with a given PLL as the clock sources.
When driving the PLL using the GCLK network, the input and output delays may not
be fully compensated in the Quartus II software.
If the data and clock arrive at the same time at the input pins, the phase relationship
between the data and clock remains the same at the data and clock ports of any I/O
element input register.
Figure 5–12
mode for source-synchronous data transfers. Data and clock signals at the I/O
element experience similar buffer delays as long as the same I/O standard is used.
Figure 5–12. Phase Relationship Between Data and Clock in Source
Source-synchronous mode compensates for delay of the clock network used,
including any difference in the delay between the following two paths:
■
■
Set the input pin to the register delay chain in the I/O element to zero in the
Quartus II software for all data pins clocked by a source-synchronous mode PLL.
Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II
software.
Data pin to I/O element register input
Clock input pin to the PLL phase frequency detector (PFD) input
shows an example waveform of the data and clock in this mode. Use this
clock at input pin
Clock at register
Data at register
PLL reference
Table 5–6 on page 5–18
Data pin
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
for Cyclone IV E PLLs.
Table 5–5 on page 5–17
© December 2010 Altera Corporation
- Synchronous Mode
Clock Feedback Modes
for
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