EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 387

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Cyclone IV Reset Control and Power Down
Power Down
Power Down
Figure 2–13. Sample Reset Sequence of a Receiver and Transmitter Channels-Receiver CDR in Automatic Lock Mode with
the Optional gxb_powerdown Signal
Notes to
(1) The gxb_powerdown signal must not be asserted during the offset cancellation sequence.
(2) For t
(3) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
© December 2010 Altera Corporation
Reset/Power Down Signals
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
Output Status Signals
LTD_Auto
Figure
gxb_powerdown
rx_analogreset
rx_digitalreset
duration, refer to the
tx_digitalreset
2–13:
rx_freqlocked
pll_areset
pll_locked
busy (3)
The Quartus II software automatically selects the power-down channel feature, which
takes effect when you configure the Cyclone IV GX device. All unused transceiver
channels and blocks are powered down to reduce overall power consumption. The
gxb_powerdown signal is an optional transceiver block signal. It powers down all
transceiver channels and all functional blocks in the transceiver block. The minimum
pulse width for this signal is 1 s. After power up, if you use the gxb_powerdown
signal, wait for deassertion of the busy signal, then assert the gxb_powerdown signal
for a minimum of 1 s. Lastly, follow the sequence shown in
The deassertion of the busy signal indicates proper completion of the offset
cancellation process on the receiver channel.
Cyclone IV Device Datasheet
(Note 1)
2
1
chapter.
1 µs
3
4
5
6
Cyclone IV Device Handbook, Volume 2
Figure
2–13.
7
t
LTD_Auto
(2)
8
2–21