EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 423

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Cyclone IV Dynamic Reconfiguration
Error Indication During Dynamic Reconfiguration
Error Indication During Dynamic Reconfiguration
© December 2010 Altera Corporation
Table 3–7. ALTGX Megafunction Port List for PLL Reconfiguration Mode (Part 2 of 2)
pll_scanclk
[n..0]
pll_scanclkena
[n..0]
pll_configupdate
[n..0]
pll_reconfig_done
[n..0]
pll_scandataout
[n..0]
Note to
(1) <n> = (number of transceiver PLLs configured in the ALTGX MegaWizard) - 1.
Port Name
Table
3–7:
f
(1)
For more information about the ALTPLL_RECONFIG megafunction port list,
description and usage, refer to the
(ALTPL_RECONFIG) Megafunction User
The ALTGX_RECONFIG MegaWizard Plug-In Manager provides an error status
signal when you select the Enable illegal mode checking option or the Enable self
recovery option in the Error checks/data rate switch screen. The conditions under
which the error signal is asserted are:
■
Enable illegal mode checking option—when you select this option, the dynamic
reconfiguration controller checks whether an attempted operation falls under one
of the conditions listed below. The dynamic reconfiguration controller detects
these conditions within two reconfig_clk cycles, deasserts the busy signal, and
asserts the error signal for two reconfig_clk cycles.
■
■
Output
Output
Output
Input/
Input
Input
Input
PMA controls, read operation—none of the output ports (rx_eqctrl_out,
rx_eqdcgain_out, tx_vodctrl_out, and tx_preemp_out) are selected
in the ALTGX_RECONFIG instance and the read signal is asserted.
PMA controls, write operation—none of the input ports (rx_eqctrl,
rx_eqdcgain, tx_vodctrl, and tx_preemp) are selected in the
ALTGX_RECONFIG instance and the write_all signal is asserted.
Drives the scanclk port on the
reconfigurable transceiver PLL.
Acts as a clock enable for the
scanclk port on the reconfigurable
transceiver PLL.
Drives the configupdate port on
the reconfigurable transceiver PLL.
This signal is asserted to indicate the
reconfiguration process is done.
This port scan out the current
configuration of the transceiver PLL.
Description
Phase-Locked Loop Reconfiguration
Guide.
Connect the pll_scanclk port of the ALTGX
megafunction to the ALTPLL_RECONFIG scanclk port.
Connect the pll_scanclkena port of the ALTGX
megafunction to the ALTPLL_RECONFIG scanclk port.
This port is connected to the pll_configupdate port
from the ALTPLL_RECONFIG controller. After the final data
bit is sent out, the ALTPLL_RECONFIG controller asserts
this signal.
Connect the pll_reconfig_done port to the
pll_scandone port on the ALTPLL_RECONFIG
controller. The transceiver PLL scandone output signal
drives this port and determines when the PLL is
reconfigured.
Connect the pll_scandataout port to the
pll_scandataout port of the ALTPLL_RECONFIG
controller. This port reads the current configuration of the
transceiver PLL and send it to the ALTPLL_RECONFIG
megafunction.
Cyclone IV Device Handbook, Volume 2
Comments
3–33