EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 51
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4CE40F29C8N
Manufacturer Part Number
EP4CE40F29C8N
Description
IC CYCLONE IV FPGA 40K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE40F29C8N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1134000
Number Of I /o
532
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE40F29C8N
Manufacturer:
ALTERA43
Quantity:
1 602
Part Number:
EP4CE40F29C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4CGX15BN11C8N PDF datasheet
- EP4CGX15BN11C8N PDF datasheet #2
- EP4CGX15BN11C8N PDF datasheet #3
- EP4CGX15BN11C8N PDF datasheet #4
- Current page: 51 of 478
- Download datasheet (13Mb)
Chapter 3: Memory Blocks in Cyclone IV Devices
Design Considerations
Read or Write Clock Mode
Single-Clock Mode
Design Considerations
Read-During-Write Operations
© November 2009 Altera Corporation
Cyclone IV devices M9K memory blocks can implement read or write clock mode for
FIFO and simple dual-port memories. In this mode, a write clock controls the data
inputs, write address, and wren registers. Similarly, a read clock controls the data
outputs, read address, and rden registers. M9K memory blocks support independent
clock enables for both the read and write clocks.
When using read or write mode, if you perform a simultaneous read or write to the
same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode, input clock mode, or output
clock mode and choose the appropriate read-during-write behavior in the
MegaWizard Plug-In Manager.
Cyclone IV devices M9K memory blocks can implement single-clock mode for FIFO,
ROM, true dual-port, simple dual-port, and single-port memories. In this mode, you
can control all registers of the M9K memory block with a single clock together with
clock enable.
This section describes designing with M9K memory blocks.
“Same-Port Read-During-Write Mode” on page 3–16
Write Mode” on page 3–17
configurations when reading from an address during a write operation at that same
address.
There are two read-during-write data flows: same-port and mixed-port.
shows the difference between these flows.
Figure 3–13. Cyclone IV Devices Read-During-Write Data Flow
write_a
read_a
Port A
data in
Port A
data out
describe the functionality of the various RAM
and
Port B
data in
Port B
data out
Cyclone IV Device Handbook, Volume 1
“Mixed-Port Read-During-
read_b
write_b
Figure 3–13
Mixed-port
data flow
Same-port
data flow
3–15
Related parts for EP4CE40F29C8N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: