EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 419
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EP4CE40F29C8N
Manufacturer Part Number
EP4CE40F29C8N
Description
IC CYCLONE IV FPGA 40K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE40F29C8N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1134000
Number Of I /o
532
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
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Price
Company:
Part Number:
EP4CE40F29C8N
Manufacturer:
ALTERA43
Quantity:
1 602
Part Number:
EP4CE40F29C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–13. Option 1 for Receiver Core Clocking (Channel Reconfiguration Mode)
© December 2010 Altera Corporation
tx_clkout[0]
FPGA Fabric
Low-speed parallel clock (tx_clkout0)
High-speed serial clock generated by the MPLL
Figure 3–13
a transceiver block.
Option 2: Use the Respective Channel Transmitter Core Clocks
■
■
Enable this option if you want the individual transmitter channel’s tx_clkout
signal to provide the read clock to its respective Receive Phase Compensation
FIFO.
This option is typically enabled when all the transceiver channels have rate
matching enabled with different data rates and are reconfigured to another Basic
or Protocol functional mode with rate matching enabled.
shows the sharing of channel 0’s tx_clkout between all four channels of
Transceiver Block
TX0
RX0
TX1
RX1
TX2
RX2
TX3
RX3
Cyclone IV Device Handbook, Volume 2
MPLL
3–29
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