EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 339

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Serial RapidIO Mode
Figure 1–60. Transceiver Channel Datapath and Clocking when Configured in Serial RapidIO Mode
Notes to
(1) Optional rate match FIFO.
(2) High-speed recovered clock.
(3) Low-speed recovered clock.
© December 2010 Altera Corporation
Fabric
FPGA
tx_clkout
Figure 1–60
1
:
Serial RapidIO mode provides the non-bonded (×1) transceiver channel datapath
configuration for SRIO protocol implementation. The Cyclone IV GX transceiver
provides the PMA and the following PCS functions:
■
■
Cyclone IV GX transceivers do not have built-in support for some PCS functions such
as pseudo-random idle sequence generation and lane alignment in ×4 bonded
channel configuration. If required, you must implement these functions in a user
logics or external circuits.
The RapidIO Trade Association defines a high-performance, packet-switched
interconnect standard to pass data and control information between microprocessors,
digital signals, communications, network processes, system memories, and peripheral
devices. The SRIO physical layer specification defines serial protocol running at
1.25 Gbps, 2.5 Gbps, and 3.125 Gbps in either single-lane (×1) or bonded four-lane (×4)
at each line rate. Cyclone IV GX transceivers support single-lane (×1) configuration at
all three line rates. Four ×1 channels configured in Serial RapidIO mode can be
instantiated to achieve one non-bonded ×4 SRIO link. When implementing four ×1
SRIO channels, the receivers do not have lane alignment or deskew capability.
Figure 1–60
Serial RapidIO mode.
8B/10B encoding and decoding
lane synchronization state machine
Phase
Comp
FIFO
Rx
shows the transceiver channel datapath and clocking when configured in
wr_clk
Tx Phase
Comp
FIFO
rd_clk
Order-
Byte
ing
serializer
/2
Byte
De-
wr_clk
Byte Serializer
/2
Transmitter Channel PCS
Decoder
8B/10B
Receiver Channel PCS
rd_clk
Match
FIFO
Rate
(1)
8B/10B Encoder
Deskew
FIFO
Cyclone IV Device Handbook, Volume 2
(3)
Aligner
Word
Deserial-
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
(2)
1–59
CDR
low-speed clock
high-speed
clock
CDR clock