EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 292

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–12
Cyclone IV Device Handbook, Volume 2
f
1
Figure 1–14
Figure 1–14. Receiver Input Buffer Block Diagram
The receiver input buffers support the following features:
■
■
■
■
■
Disable OCT to use external termination if the link requires a 85  termination, such
as when you are interfacing with certain PCIe Gen1 or Gen2 capable devices.
For specifications on programmable equalization and DC gain settings, refer to the
Cyclone IV Device Data
Programmable equalization—boosts the high-frequency gain of the incoming
signal up to 7 dB. This compensates for the low-pass filter effects of the
transmission media. The amount of high-frequency gain required depends on the
loss characteristics of the physical medium.
Programmable DC gain—provides equal boost to incoming signal across the
frequency spectrum with DC gain settings up to 6 dB.
Programmable differential OCT—provides calibrated OCT at 100  or 150 with
on-chip receiver common mode voltage at 0.82 V. The common mode voltage is tri-
stated when you disable the OCT to use external termination.
Offset cancellation—corrects the analog offset voltages that might exist from
process variations between the positive and negative differential signals in the
equalizer stage and CDR circuit.
Signal detection—detects if the signal level present at the receiver input buffer is
higher than the threshold with a built-in signal threshold detection circuitry. The
circuitry has a hysteresis response that filters out any high-frequency ringing
caused by ISI effects or high-frequency losses in the transmission medium.
Detection is indicated by the assertion of the rx_signaldetect signal. Signal
detection is only supported when 8B/10B encoder/decoder block is enabled.
When not supported, the rx_signaldetect signal is forced high, bypassing the
signal detection function.
rx_datain
50 or 75 
shows the receiver input buffer block diagram.
Receiver Input Buffer
RX
V
CM
Sheet.
50  or 75 
Equalization
Threshold
Detection
DC Gain
Circuitry
Circuitry
Signal
and
Chapter 1: Cyclone IV Transceivers Architecture
© December 2010 Altera Corporation
Receiver Channel Datapath
To CDR
Detect
Signal