EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 298

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–18
Cyclone IV Device Handbook, Volume 2
Table 1–4
this mode.
Table 1–4. Synchronization State Machine Parameters
After deassertion of the rx_digitalreset signal in automatic synchronization state
machine mode, the word aligner starts looking for the word alignment pattern or
synchronization code groups in the received data stream. When the programmed
number of valid synchronization code groups or ordered sets are received, the
rx_syncstatus signal is driven high to indicate that synchronization is acquired.
The rx_syncstatus signal is constantly driven high until the programmed number
of erroneous code groups are received without receiving intermediate good groups;
after which the rx_syncstatus signal is driven low. The word aligner indicates loss
of synchronization (rx_syncstatus signal remains low) until the programmed
number of valid synchronization code groups are received again.
In addition to restoring word boundaries, the word aligner supports the following
features:
■
Table 1–5. Run Length Violation Circuit Detection Capabilities
■
Number of valid synchronization code groups or ordered sets
received to achieve synchronization
Number of erroneous code groups received to lose
synchronization
Number of continuous good code groups received to reduce
the error count by one
Supported Data Width
Programmable run length violation detection—detects consecutive 1s or 0s in the
data stream, and asserts run length violation signal (rx_rlv) when a preset run
length threshold (maximum number of consecutive 1s or 0s) is detected. The
rx_rlv signal in each channel is clocked by its parallel recovered clock and is
asserted for a minimum of two recovered clock cycles to ensure that the FPGA
fabric clock can latch the rx_rlv signal reliably because the FPGA fabric clock
might have phase differences, PPM differences (in asynchronous systems), or both,
with the recovered clock.
capabilities.
Receiver polarity inversion—corrects accidental swapped positive and negative
signals from the serial differential link during board layout. This feature works by
inverting the polarity of every bit of the input data word to the word aligner,
which has the same effect as swapping the positive and negative signals of the
differential link. Inversion is dynamically controlled using rx_invpolarity
port.
10-bit
8-bit
Figure 1–19
lists the synchronization state machine parameters for the word aligner in
shows the receiver polarity inversion feature.
Parameter
Minimum
Table 1–5
4
5
Detector Range
lists the run length violation circuit detection
Chapter 1: Cyclone IV Transceivers Architecture
Maximum
128
160
© December 2010 Altera Corporation
Allowed Values
1–256
1–256
1–64
Receiver Channel Datapath
Increment Step
Settings
4
5