EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 396

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

3–6
Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 4 of 6)
Cyclone IV Device Handbook, Volume 2
tx_preemp[4..0]
(1)
rx_eqctrl[3..0]
(1)
Port Name
Output
Input/
Input
Input
This is an optional pre-emphasis write control for the transmit buffer. Depending on what value
you set at this input, the controller dynamically writes the value to the pre-emphasis control
register of the transmit buffer.
The width of this signal is fixed to 5 bits if you enable either the Use 'logical_channel_address'
port for Analog controls reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the width of this signal is 5 bits per
channel.
tx_preemp[4..0]
00000
00001
00101
01001
01101
10000
10001
10010
10011
10100
10101
All other values => N/A
This is an optional write control to write an equalization control value for the receive side of the
PMA.
The width of this signal is fixed to 4 bits if you enable either the Use 'logical_channel_address'
port for Analog controls reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the width of this signal is 4 bits per
channel.
rx_eqctrl[3..0]
0001
0101
0111
All other values => N/A
0100
Corresponding ALTGX
Corresponding ALTGX instance settings
Low
Medium Low
High
Medium High
instance settings
13
16
17
18
19
20
21
0
1
5
9
Description
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Controller Port List
© December 2010 Altera Corporation
emphasis setting (mA)
Corresponding pre-
Disabled
0.5
1.0
1.5
2.0
2.375
2.5
2.625
2.75
2.875
3.0