EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 219

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
Figure 8–28. Combining JTAG and AS Configuration Schemes
Notes to
(1) Connect these pull-up resistors to the V
(2) Power up the V
(3) Pin 6 of the header is a V
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL for AS
(5) Power up the V
(6) You must place the diodes and capacitors as close as possible to the Cyclone IV device. Altera recommends using
(7) These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin
(8) Resistor value can vary from 1 k to 10 k..
(9) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for
device. For this value, refer to the
ByteBlasterMV download cable, this pin is a no connect. When using the USB-Blaster and ByteBlaster II cables, this
pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.
configuration schemes, refer to
the MSEL pins directly to V
Third-party programmers must switch to 2.5 V. Pin 4 of the header is a V
The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V from
the USB cable. For this value, refer to the
the Schottky diode, which has a relatively lower forward diode voltage (VF) than the switching and Zener diodes, for
effective voltage clamping.
functions as DATA[1] pin in AP and FPP modes.
DCLK.
10-Pin Male Header
Download Cable
Figure
Configuration
(AS Mode)
Pin 1
Device
Serial
DCLK
DATA
ASDI
8–28:
nCS
3.3 V (2)
CC
CC
10 kΩ
10kΩ
of the EthernetBlaster, ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5-V V
of the EthernetBlaster, ByteBlaster II, or USB-Blaster cable with the 3.3-V supply.
V
CCIO
GND
IO
(1)
10 kΩ
reference voltage for the MasterBlaster output driver.The V
CCA
V
10 pf
(6)
CCIO
or GND.
Table 8–3 on page
(6)
GND
MasterBlaster Serial/USB Communications Cable User
3.3 V
(1)
10 kΩ
GND
3.3 V
V
CCIO
CCIO
MasterBlaster Serial/USB Communications Cable User
GND
3.3 V
10 pf
supply of the bank in which the pin resides.
(1)
10 pf
3.3 V
GND
8–8,
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
nCSO (7)
ASDO (7)
10 pf
Table 8–4 on page
Cyclone IV Device
CLKUSR
MSEL[ ]
nCEO
TCK
TDO
TMS
TDI
CC
8–8, and
power supply for the MasterBlaster cable.
Cyclone IV Device Handbook, Volume 1
N.C.
(9)
(4)
V
CCA
Table 8–5 on page
(8)
V
IO
CCA
1 kΩ
must match the V
Guide. When using the
(8)
GND
10-Pin Male Header
Pin 1
Download Cable
Guide.
(JTAG Mode)
(top view)
8–9. Connect
CCA
V
CCA
CCA
supply.
V
of the
IO
8–53
(5)
(3)