EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 194

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–28
Figure 8–10. AP Configuration with Multiple Bus Masters
Notes to
(1) Connect the pull-up resistors to the V
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0], refer to
(4) The AP configuration ignores the WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic,
(5) When cascading Cyclone IV E devices in a multi-device AP configuration, connect the repeater buffers between the master device and slave
(6) The other master device must fit the maximum overshoot equation outlined in
(7) The other master device can control the AP configuration bus by driving the nCE to high with an output high on the I/O pin.
(8) The other master device can pulse nCONFIG if it is under system control and not tied to V
Cyclone IV Device Handbook, Volume 1
page
you can optionally use the normal I/O to monitor the WAIT signal from the Numonyx P30 or P33 flash.
devices for DATA[15..0] and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers
must fit the maximum overshoot equation outlined in
Figure
8–9. Connect the MSEL pins directly to V
8–10:
Numonyx P30/P33 Flash
Figure 8–10
DQ[15:0]
A[24:1]
CCIO
RST#
ADV#
WAIT
WE#
OE#
CLK
CE#
shows the AP configuration with multiple bus masters.
supply of the bank in which the pin resides.
CCA
or GND.
Other Master Device
“Configuration and JTAG Pin I/O Requirements” on page
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
(6)
10 k
“Configuration and JTAG Pin I/O Requirements” on page
GND
10 k
V
CCIO
nCE
DCLK (5)
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O (4)
DATA[15..0] (5)
PADD[23..0]
CCIO
(1)
.
10 k
Master Device
Cyclone IV E
V
CCIO
(1)
© December 2010 Altera Corporation
MSEL[3..0]
10 k
V
nCEO
8–5.
CCIO
(1)
(2)
(3)
Table 8–5 on
Configuration
8–5.