EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 101

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
Clock Networks in Arria II GX Devices
© July 2010
Altera Corporation
1
Figure 5–5. RCLK Control Block
Note to
(1) This clock select signal can only be statically controlled through a configuration file (.sof or .pof) and cannot be
You can statically control the clock source selection for the regional clock select block
with configuration bit settings in the configuration file (.sof or .pof) generated by the
Quartus II software.
You can power down the Arria II GX clock networks both statically and dynamically.
When a clock network is powered down, all the logic fed by the clock network is in an
off-state, thereby reducing the overall power consumption of the device. The unused
GCLK and RCLK networks are automatically powered down through configuration
bit settings in the configuration file (.sof or .pof) generated by the Quartus II software.
The dynamic clock enable or disable feature allows the internal logic to control power-
up or power-down synchronously on GCLK and RCLK networks. This function is
independent of the PLL and is applied directly on the clock network, as shown in
Figure 5–4
You can set the input clock sources and the clkena signals for the GCLK and RCLK
clock network multiplexers through the Quartus II software with the ALTCLKCTRL
megafunction. You can also enable or disable the dedicated external clock output pins
with the ALTCLKCTRL megafunction.
clock control block.
When you use the ALTCLKCTRL megafunction to implement dynamic clock source
selection in Arria II GX devices, the inputs from the clock pins, except for the left side
of the device, feed the inclk[0..1] ports of the multiplexer, and the PLL outputs
feed the inclk[2..3]ports. You can choose from among these inputs with the
CLKSELECT[1..0]signal. For the connections between the PLL counter outputs to
the clock control block on the left side of the Arria II GX device, refer to
dynamically controlled during user mode operation.
Figure
and
5–5:
Figure
PLL Counter
5–5.
Outputs
2
CLK
Pin
Enable/
Disable
Figure 5–6
RCLK
Internal
Logic
Static Clock Select (1)
shows the external PLL output
Internal
Logic
Arria II GX Device Handbook, Volume 1
Table
5–7.
5–9