EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 115

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
Programmable Phase Shift
© July 2010
Altera Corporation
Phase shift is used to implement a robust solution for clock delays in Arria II GX
devices. Phase shift is implemented with a combination of the VCO phase output and
the counter starting time. The VCO phase output and counter starting time
combination is the most accurate method of inserting delays because it is purely
based on counter settings, which are independent of process, voltage, and
temperature (PVT).
You can phase-shift the output clocks from the Arria II GX PLLs in either of these two
resolutions:
■
■
Fine-resolution phase shifts are implemented by allowing any of the output counters
(C[n..0]) or the m counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution. The minimum
delay time that you can insert with this method is defined by:
Equation 5–1. Fine-Resolution Phase Shifts
where f
For example, if f
156.25 ps. This phase shift is defined by the PLL operating frequency, which is
governed by the reference clock frequency and the counter settings.
Coarse-resolution phase shifts are implemented by delaying the start of the counters
for a predetermined number of counter clocks. You can express coarse phase shift as:
Equation 5–2. Coarse-Resolution Phase Shifts
where C is the count value set for the counter delay time, (this is the initial setting in
the PLL usage section of the compilation report in the Quartus II software). If the
initial value is 1, C – 1 = 0° phase shift.
Figure 5–18
the VCO phase taps method. The eight phases from the VCO are shown and labeled
for reference. For this example, CLK0 is based off the 0phase from the VCO and has
the C value for the counter set to one. The CLK1 signal is divided by four, two VCO
clocks for high time and two VCO clocks for low time. CLK1 is based off the
135× phase tap from the VCO and also has the C value for the counter set to one. The
CLK1 signal is also divided by four. In this case, the two clocks are offset by 3 
CLK2 is based off the 0phase from the VCO but has the C value for the counter set to
three. This arrangement creates a delay of 2 
Fine resolution with VCO phase taps
Coarse resolution with counter starting time
REF
is the input reference clock frequency.
shows an example of phase-shift insertion with the fine resolution with
REF
is 100 MHz, n is 1, and m is 8, then f
Φ
fine
=
1
8
T
VCO
Φ
coarse
=
8f
=
VCO
1
C − 1
f
=
V
co
8Mf
N
COARSE
=
REF
(C − 1)N
Mf
(two complete VCO periods).
REF
VCO
Arria II GX Device Handbook, Volume 1
is 800 MHz and 
fine
equals
fine
.
5–23