EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 54

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–14
Figure 3–16. Arria II GX Shift-Register Memory Configuration
ROM Mode
FIFO Mode
Arria II GX Device Handbook, Volume 1
f
w × m × n Shift Register
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Figure 3–16
All Arria II GX memory blocks support ROM mode. A memory initialization file
(.mif) initializes the ROM contents of these blocks. The address lines of the ROM are
registered on M9K blocks, but can be unregistered on MLABs. The outputs can be
registered or unregistered. Output registers can be asynchronously cleared. The ROM
read operation is identical to the read operation in the single-port RAM configuration.
All memory blocks support FIFO mode. MLABs are ideal for designs with many
small, shallow FIFO buffers. To implement FIFO buffers in your design, you can use
the FIFO MegaWizard Plug-In Manager in the Quartus II software. Both single- and
dual-clock (asynchronous) FIFOs are supported.
For more information about implementing FIFO buffers, refer to the
DCFIFO Megafunctions User
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
shows the memory block in shift-register mode.
Guide.
Chapter 3: Memory Blocks in Arria II GX Devices
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© November 2009 Altera Corporation
n Number of Taps
SCFIFO and
Memory Modes