EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 302

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

12–2
Table 12–1. Arria II GX Power Supply Requirements (Part 2 of 2)
Power-On Reset Circuitry
Arria II GX Device Handbook, Volume 1
VCCIO
VREF
VCCBAT
VCCA
VCCH_GXB
VCCL_GXB
GND
Note to
(1) VCCA_PLL must be powered up even if the PLL is not used.
Power Supply Pin
Table
12–1:
f
f
The Arria II GX power-on reset (POR) circuitry generates a POR signal to keep the
device in the reset state until the power supply’s voltage levels have stabilized during
power-up. The POR circuitry monitors V
banks 3C and 8C, where the configuration pins are located. The POR circuitry
tri-states all user I/O pins until the power supplies reach the recommended operating
levels. These power supplies are required to monotonically reach their full-rail values
without plateaus and within the maximum power supply ramp time (t
POR circuitry de-asserts the POR signal after the power supplies reach their full-rail
values to release the device from the reset state. On power down, brown-out occurs if
the V
threshold voltage.
POR circuitry is important to ensure that all the circuits in the Arria II GX device are at
certain known states during power up. You can select the POR signal pulse width
between fast POR time or standard POR time using the MSEL pin settings. For fast
POR time, the POR signal pulse width is set to 4 ms for the power supplies to ramp up
to full rail. For standard POR time, the POR signal pulse width is set to 100 ms for the
power supplies to ramp up to full rail. In both cases, you can extend the POR time
with an external component to assert the nSTATUS pin low.
For more information about the POR specification, refer to the
Datasheet.
For more information about MSEL pin settings, refer to the
Security, and Remote System Upgrades in Arria II GX Devices
Nominal Voltage Level (V)
0.6 V, 0.75 V, 0.9 V, 1.25 V
CC
1.2 V, 1.5 V, 1.8 V,
, V
2.5 V, 3.0 V, 3.3 V
1.2 V–3.3 V
CCA_PLL
2.5 V
1.5 V
1.1 V
0 V
, V
CCCB
, V
CCPD
, and V
Supplies power to the I/O banks
Reference voltage for the voltage-referenced I/O standards
Battery back-up power supply for the design security volatile key
register
Supplies power to the transceiver PMA regulator
Supplies power to the transceiver PMA output (TX) buffer
Supplies power to the transceiver PMA TX, PMA RX, and clocking
Ground
CCIO
for I/O banks 3C and 8C drops below the
CC
, V
Chapter 12: Power Requirements for Arria II GX Devices
CCA_PLL
, V
Description
CCCB
, V
chapter.
Configuration, Design
CCPD
© July 2010 Altera Corporation
Arria II GX Device
, and V
Power-On Reset Circuitry
RAMP
CCIO
for I/O
.). The