EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 228

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–8
Fast Passive Parallel Configuration
FPP Configuration Using a MAX II as an External Host
Arria II GX Device Handbook, Volume 1
f
1
Use the data in
configuration file formats, such as a hexidecimal (.hex) or tabular text file (.ttf) format,
have different file sizes. For the different types of configuration file and file sizes, refer
to the Quartus II software. However, for specific version of the Quartus II software,
any design targeted for the same device has the same uncompressed configuration file
size. If you are using compression, the file size can vary after each compilation
because the compression ratio depends on your design.
For more information about setting device configuration options or creating
configuration files, refer to the
Formats
FPP configuration in Arria II GX devices is designed to meet the continuously
increasing demand for faster configuration times. Arria II GX devices are designed
with the capability of receiving byte-wide configuration data per clock cycle.
You can perform FPP configuration of Arria II GX devices using an intelligent host
such as a MAX II device or microprocessor.
FPP configuration using compression and an external host provides the fastest
method to configure Arria II GX devices. In this configuration scheme, you can use a
MAX II device or microprocessor as an intelligent host that controls the transfer of
configuration data from a storage device, such as flash memory, to the target
Arria II GX device. You can store configuration data in .rbf, .hex, or .ttf format. When
using the MAX II device or microprocessor as an intelligent host, a design that
controls the configuration process, such as fetching the data from flash memory and
sending it to the device, must be stored in the MAX II device or microprocessor.
If you use the Arria II GX decompression and/or design security features, the external
host must send a DCLK frequency that is ×4 the data rate in bytes per second (Bps).
The ×4 DCLK signal does not require an additional pin and is sent on the DCLK pin.
The maximum DCLK frequency is 125 MHz, which results in a maximum data rate of
250 Mbps. If you do not use the Arria II GX decompression or design security
features, the DCLK frequency is ×1 the data rate in Bps.
chapters in volume 2 of the Configuration Handbook.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Table 9–3
to estimate the file size before design compilation. Different
Device Configuration Options
and
Fast Passive Parallel Configuration
© July 2010 Altera Corporation
Configuration File