EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 137
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 6: I/O Features in Arria II GX Devices
Arria II GX I/O Banks
Arria II GX I/O Banks
Figure 6–1. Arria II GX Devices I/0 Banks
Notes to
(1) Banks GXB0, GXB1, GXB2, and GXB3 are dedicated banks for high-speed transceiver I/Os.
(2) Banks 3C and 8C are dedicated configuration banks and do not have user I/O pins.
(3) LVDS with DPA is supported at banks 5A, 5B, 6A, and 6B.
(4) Differential HSTL and SSTL inputs use LVDS differential input buffers without R
(5) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
(6)
(7) The PLL_CLKOUT pin supports only emulated differential I/O standard but not true differential I/O standard.
© July 2010 Altera Corporation
inverted.
Figure 6–1
Figure
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
6–1:
Arria II GX devices contain up to 16 I/O banks, as shown in
I/O banks contain high-speed transceiver banks, with dedicated configuration banks
at banks 3C and 8C. The rest of the banks are user I/O banks. All user I/O banks
support all single-ended and differential I/O standards.
Bank 8C
Bank 3C
True LVDS, Emulated LVDS, BLVDS, RSDS, mini-LVDS,
3.3-V LVTTL/LVCMOS, 3.0-V LVTTL/LVCMOS,
2.5-V LVTTL/LVCMOS, 1.8-V LVTTL/LVCMOS,
Differential HSTL-15, and Differential HSTL-12
Differential SSTL-15, Differential HSTL-18,
Differential SSTL-2, Differenital SSTL-18,
Bank 8B
Bank 3B
(Note
1.5-V LVCMOS, 1.2-V LVCMOS,
HSTL-18, HSTL-15, HSTL-12,
SSTL-2, SSTL-18, SSTL-15,
These I/O Banks Support:
1), (2), (3), (4), (5), (6),
Bank 8A
Bank 3A
D
Bank 7A
Bank 4A
OCT support.
(7)
Bank 7B
Bank 4B
Arria II GX Device Handbook, Volume 1
Figure
6–1. The left side
6–3
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