EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 130

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–38
Figure 5–28. Dynamic Phase Shifting Waveform
PLL Specifications
Arria II GX Device Handbook, Volume 1
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
f
f
The phasestep signal is latched on the negative edge of scanclk. In
this is shown by the second scanclk falling edge. phasestep must stay high for at
least two scanclk cycles. On the second scanclk rising edge after phasestep is
latched (the fourth scanclk rising edge in
and phasecounterselect are latched and the PLL starts dynamic phase-shifting
for the specified counters and in the indicated direction. On the fourth scanclk
rising edge, phasedone goes high to low and remains low until the PLL finishes
dynamic phase-shifting. You can perform another dynamic phase-shift after the
phasedone signal goes from low to high.
Depending on the VCO and scanclk frequencies, phasedone low time
(t
For more information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager
interface, refer to the
Megafunction User
For more information about PLL timing specifications, refer to the
Datasheet.
a
CONFIGPHASE
b
t
CONFIGPHASE
PHASEDONE goes low synchronous with SCANCLK
) may be greater than or less than one scanclk cycle.
Guide.
Phase Locked-Loops Reconfiguration (ALTPLL_RECONFIG)
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
Figure
c
5–28), the values of phaseupdown
d
© July 2010 Altera Corporation
PLLs in Arria II GX Devices
Arria II GX Devices
Figure
5–28,