EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 206

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–22
Receiver Skew Margin for Non-DPA Mode
Arria II GX Device Handbook, Volume 1
Changes in system environment, such as temperature, media (cable, connector, or
PCB), and loading, effect the receiver ’s setup and hold times; internal skew affects the
sampling ability of the receiver.
Different modes of LVDS receivers use different specifications, which can help in
deciding the ability to sample the received serial data correctly. In DPA mode, use
DPA jitter tolerance instead of receiver skew margin (RSKM).
In non-DPA mode, use RSKM, transmitter channel-to-channel skew (TCCS), and
sampling window (SW) specifications for high-speed source-synchronous differential
signals in the receiver datapath. The relationship between RSKM, TCCS, and SW is
expressed by the RSKM equation shown in
Equation 8–1.
Where:
■
■
■
■
You must calculate the RSKM value to decide whether or not data can be sampled
properly by the LVDS receiver with the given data rate and device. A positive RSKM
value indicates the LVDS receiver can sample the data properly; a negative RSKM
indicates the receiver cannot sample the data properly.
Figure 8–20
Figure 8–20. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA
For LVDS receivers, the Quartus II software provides the RSKM report showing SW,
TUI, and RSKM values for non-DPA mode. You can generate the RSKM by executing
the report_RSKM command in the TimeQuest Timing Analyzer. You can find the
RSKM report in the Quartus II Compilation report under TimeQuest Timing
Analyzer section.
TUI—the time period of the serial data.
RSKM—the timing margin between the receiver’s clock input and the data input
SW.
SW—the period of time that the input data must be stable to ensure that data is
successfully sampled by the LVDS receiver. The sampling window is device
property and varies with device speed grade.
TCCS—the difference between the fastest and slowest data output transitions,
including the t
shows the relationship between the RSKM, TCCS, and SW.
Internal Clock
Input Clock
Input Data
Receiver
External
CO
variation and clock skew.
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
TCCS
RSKM = (TUI - SW - TCCS)/2
RSKM
Time Unit Interval (TUI)
Sampling Window (SW)
Equation
8–1:
RSKM
Source-Synchronous Timing Budget
© July 2010 Altera Corporation
TCCS