EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 205
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Source-Synchronous Timing Budget
Figure 8–19. Bit Order and Word Boundary for One Differential Channel
Note to
(1) These are only functional waveforms and are not intended to convey timing information.
© July 2010
Transmitter Channel
Operation (x8 Mode)
Operation (x8 Mode)
Receiver Channel
rx_out [7..0]
tx_outclock
rx_outclock
rx_inclock
Figure
tx_out
rx_in
Altera Corporation
8–19:
X
7
X X X X X X X
6
X X X X X X X X
Table 8–6
The MSB and LSB positions increase with the number of channels used in a system.
Table 8–6. Differential Bit Naming
5
Previous Cycle
4
Receiver Channel Data
3
2
lists the conventions for differential bit naming for 18 differential channels.
Number
1
10
11
12
13
14
15
16
17
18
0
1
2
3
4
5
6
7
8
9
MSB
7
X
6
X
Current Cycle
5
X X X X X X X X
X
4 3
X
X
2
X
1
LSB
X
0
X X X
X
MSB Position
Next Cycle
X
103
111
119
127
135
143
X
15
23
31
39
47
55
63
71
79
87
95
7
(Note 1)
X X X X 7 6 5 4
X X X X X
X
Internal 8-Bit Parallel Data
X
X
X
X
Arria II GX Device Handbook, Volume 1
X
X
X
X
LSB Position
3 2 1 0 X X X X
X
104
112
120
128
136
16
24
32
40
48
56
64
72
80
88
96
0
8
X
X
X
X
8–21
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