EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 204
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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8–20
Source-Synchronous Timing Budget
Differential Data Orientation
Differential I/O Bit Position
Arria II GX Device Handbook, Volume 1
This section describes the timing budget, waveforms, and specifications for
source-synchronous signaling in the Arria II GX devices. Timing analysis for the
differential block is different from traditional synchronous timing analysis techniques.
Therefore, it is important to understand how to analyze timing for high-speed
differential signals. This section defines the source-synchronous differential data
orientation timing parameters, timing budget definitions, and how to use these timing
parameters to determine your design’s maximum performance.
There is a set relationship between an external clock and the incoming data. For
operation at 1 Gbps and a serialization factor of 10, the external clock is multiplied
by 10. You can set the phase-alignment in the PLL to coincide with the sampling
window of each data bit. The data is sampled on the falling edge of the multiplied
clock.
Figure 8–18
Figure 8–18. Bit Orientation
Data synchronization is necessary for successful data transmission at high
frequencies.
figures are based on the following:
■
■
■
For other serialization factors, use the Quartus II software tools and find the bit
position in the word. The bit positions after deserialization are listed in
Serialization factor equals clock multiplication factor
Edge alignment is selected for phase alignment
Implemented in hard SERDES
inclock/outclock
shows the data bit orientation of the ×10 mode.
Figure 8–19
data in
shows data bit orientation for a channel operation. These
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
MSB
9
8
7
6
10 LVDS Bits
5
4
3
Source-Synchronous Timing Budget
© July 2010 Altera Corporation
2
1
LSB
0
Table
8–6.
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