EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 48

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–8
Single-Port RAM
Arria II GX Device Handbook, Volume 1
1
When using the memory blocks in ROM, single-port, simple dual-port, or true
dual-port mode, you can corrupt the memory contents if you violate the setup or hold
time on any of the memory block input registers. This applies to both read and write
operations.
All memory blocks support single-port mode. Single-port mode allows you to do
either one-read or one-write operation at a time. Simultaneous reads and writes are
not supported in single-port mode.
configuration.
Figure 3–8. Single-Port Memory
Note to
(1) You can implement two single-port memory blocks in a single M9K block. For more information, refer to
During a write operation, behavior of the RAM outputs is configurable. If you use the
read-enable signal and perform a write operation with the read enable de-activated,
the RAM outputs retain the values they held during the most recent active read
enable. If you activate read enable during a write operation, or if you are not using the
read-enable signal at all, the RAM outputs either show the new data being written,
the old data at that address, or a don’t care value.
Table 3–3
mode.
Table 3–3. Arria II GX Port Width Configurations for MLABs and M9K Blocks
Mode Support” on page
Figure
lists the possible port width configurations for memory blocks in single-port
3–8:
64 × 10
32 × 16
32 × 18
32 × 20
MLABs
64 × 8
64 × 9
3–4.
data[ ]
address[ ]
wren
byteena[]
addressstall
clockena
rden
aclr
inclock
(Note 1)
Figure 3–8
shows the single-port RAM
M9K Blocks
Chapter 3: Memory Blocks in Arria II GX Devices
512 × 16
512 × 18
256 × 32
256 × 36
8K × 1
4K × 2
2K × 4
1K × 8
1K × 9
outclock
© November 2009 Altera Corporation
q[]
Memory Modes
“Packed