EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 217

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Setting Up an LVDS Transmitter or Receiver Channel
Setting Up an LVDS Transmitter or Receiver Channel
© July 2010
Altera Corporation
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Using Both Corner PLLs
You can use both corner PLLs to drive DPA disabled channels simultaneously. Both
corner PLLs can drive cross-banks.
You can use a corner PLL to drive all the transmitter channels and you can use the
other corner PLL to drive all DPA-disabled receiver channels in the same I/O bank.
Both corner PLLs can drive duplex channels in the same I/O bank, as long as the
channels driven by each PLL are not interleaved. No separation is necessary between
the group of channels driven by both corner PLLs.
The ALTLVDS megafunction offers you the ease of setting up an LVDS transmitter or
receiver channel. You can control the settings of SERDES and DPA circuitry in the
ALTLVDS megafunction. When you instantiate an ALTLVDS megafunction, the PLL
is instantiated automatically and you can set the parameters of the PLL. This
simplifies the clocking setup for the LVDS transmitter or receiver channels. However,
the drawback is reduced flexibility when using the PLL.
The ALTLVDS megafunction provides an option for implementing the LVDS
transmitter or receiver interfaces with external PLLs. With this option enabled, you
can control the PLL settings, such as dynamically reconfiguring the PLLs to support
different data rates, dynamic phase shift, and other settings. You also must instantiate
an ALTPLL megafunction to generate the various clock and load enable signals.
For more information about how to control the PLL, SERDES, and DPA settings, and
detailed descriptions of the LVDS transmitter and receiver interface signals, refer to
the
For more information about the ALTPLL megafunction, refer to the
(ALTPLL) Megafunction User
SERDES Transmitter/Receiver (ALTLVDS) Megafunction User
Guide.
Arria II GX Device Handbook, Volume 1
Guide.
Phase Locked-Loops
8–33