EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 207

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Pin Placement Guidelines
Differential Pin Placement Guidelines
DPA-Enabled Channels and Single-Ended I/Os
Guidelines for DPA-Enabled Differential Channels
© July 2010
Altera Corporation
f
1
1
To obtain the RSKM value, assign an appropriate input delay to the LVDS receiver
through the TimeQuest Timing Analyzer constraints menu.
To ensure proper high-speed operation, differential pin placement guidelines are
established. The Quartus II Compiler automatically checks that these guidelines are
followed and issues an error message if they are not adhered to. This section is
divided into pin placement guidelines with and without DPA usage.
DPA-enabled differential channels refer to DPA mode or soft CDR mode;
DPA-disabled channels refer to non-DPA mode.
When single-ended I/Os and LVDS I/Os share the same I/O bank, the placement of
single-ended I/O pins with respect to LVDS I/O pins is restricted. The constraints on
single-ended I/Os placement with respect to DPA-enabled or DPA-disabled LVDS
I/Os are the same.
For more information about pin placement with respect to LVDS, mini-LVDS, and
RSDS, refer to the
When you use DPA-enabled channels, you must adhere to the guidelines listed in the
following sections.
DPA-Enabled Channel Driving Distance
If the number of DPA-enabled channels driven by each center or corner PLL exceeds
25 logic array blocks (LAB) rows, Altera recommends implementing data realignment
(bit slip) circuitry for all the DPA channels.
Using Center and Corner PLLs
If the DPA-enabled channels in a bank are being driven by two PLLs, where the corner
PLL is driving one group and the center PLL is driving another group, there must be
at least one row of separation between the two groups of DPA-enabled channels, as
shown in
operate at independent frequencies.
No separation is necessary if a single PLL is driving both the DPA-enabled channels
and DPA-disabled channels.
Figure
8–21. This is to prevent noise mixing because the two groups can
I/O Management
chapter in volume 2 of the Quartus II Handbook.
Arria II GX Device Handbook, Volume 1
8–23