EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 84

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–24
Figure 4–14. High-Precision Multiplier Adder Configuration for Half-DSP Block
Note to
(1) Block output for accumulator overflow and saturate overflow.
Arria II GX Device Handbook, Volume 1
Figure
dataA[0:17]
dataB[0:17]
dataA[0:17]
dataB[18:35]
dataC[0:17]
dataD[0:17]
dataC[0:17]
dataD[18:35]
4–14:
In these situations, the datapath can be up to 36 bits, allowing sufficient capacity for
bit growth or gain changes in the signal source without loss of precision, which is
useful in single precision block floating point applications. As shown in
the high-precision multiplier is performed in two stages. The sum of the results of the
two adders produce the final result:
Z[54..0] = P
where:
P
0
= A[17..0] × B[35..0] and P
Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
0
[53..0] + P
<<18
<<18
1
[53..0]
+
+
1
P 0
P 1
= C[17..0] × D[35..0]
signa
signb
+
Chapter 4: DSP Blocks in Arria II GX Devices
overflow (1)
© July 2010 Altera Corporation
Operational Mode Descriptions
result[ ]
Figure
4–14,