EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 184

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–26
Revision History
Table 7–6. Document Revision History
Arria II GX Device Handbook, Volume 1
July 2010
November 2009
June 2009
February 2009
February 2009
Date
Version
Table 7–6
3.0
2.0
1.2
1.1
1.0
shows the revision history for this chapter.
Updated for Arria II GX v10.0 release:
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Updated for Arria II GX v9.1 release:
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Updated Table 7–1 and Table 7–2.
Initial release.
Updated
the
Handbook and removing “Table 7–1: Memory Interface Pin Utilization”.
Update DLL numbering to match with the Quartus II software.
Minor text edits.
Updated Table 7–1, Table 7–2, and Table 7–5.
Updated Figure 7–1, Figure 7–2, Figure 7–3, Figure 7–11, Figure 7–12, Figure 7–13,
Figure 7–15, and Figure 7–16.
Updated the “Arria II GX External Memory Interface Features” section.
Added new “Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM
Interface” section.
Minor text edits.
Added Table 7–2.
Updated Table 7–1, Table 7–3, and Table 7–5.
Updated Figure 7–1, Figure 7–3, Figure 7–4, Figure 7–5, Figure 7–6, Figure 7–7,
Figure 7–8, Figure 7–9, and Figure 7–11.
Updated “Introduction” and “DLL” sections.
Section I. Device and Pin Planning
“Arria II GX Memory Interfaces Pin Support”
Chapter 7: External Memory Interfaces in Arria II GX Devices
Changes Made
in volume 2 of the External Memory Interface
section by adding reference to
© July 2010 Altera Corporation
Revision History