EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 105

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
© July 2010
Altera Corporation
f
1
Arria II GX devices offer up to six PLLs per device and seven outputs per PLL that
provide robust clock management and synthesis for device clock management,
external system clock management, and high-speed I/O interfaces. The nomenclature
for the PLLs follows their geographical location in the device floor plan. For the
location and number of PLLs in Arria II GX devices, refer to
Figure
Depending on package, Arria II GX devices offer up to eight transceiver transmitter
(TX) PLLs per device that can be used by the FPGA fabric if they are not used by the
transceiver.
For more information about the number of general-purpose and transceiver TX PLLs
in each device density, refer to the
more information about using the transceiver TX PLLs in the transceiver block, refer
to the
All Arria II GX PLLs have the same core analog structure and support features.
Table 5–8
Table 5–8. Arria II GX PLL Features (Part 1 of 2)
C (output) counters
M, N, C counter sizes
Dedicated clock outputs
Clock input pins
External feedback input pin
Spread-spectrum input clock tracking
PLL cascading
Compensation modes
PLL drives DIFFCLK and LOADEN
VCO output drives DPA clock
Phase shift resolution
Programmable duty cycle
Output counter cascading
Arria II GX Transceiver Clocking
5–2.
lists the PLL features in Arria II GX devices.
Feature
(1)
Arria II GX Device Family Overview
7
1 to 512
1 single-ended or 1 differential pair
3 single-ended or 3 differential pairs
4 single-ended or 2 differential pin pairs
No
Yes
Through GCLK and RCLK and dedicated path between
adjacent PLLs. Cascading between the general-purpose
PLL and transceiver PLL is supported in PLL_1 and
PLL_4.
All except external feedback mode when you use
differential I/Os
Yes
Yes
Down to 96.125 ps
Yes
Yes
chapter.
(3)
(4)
Arria II GX PLLs
Arria II GX Device Handbook, Volume 1
Figure 5–1
(2)
chapter. For
and
5–13