Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 103
![IC 10MHZ Z180 CMOS ENH MPU 64DIP](/photos/6/76/67665/z8018010psg_sml.jpg)
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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88
Refresh Control Register (RCR: 36H)
UM005003-0703
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
6
1
–
Z8018x
Family MPU User Manual
0
REFE
REFW
CYC1
REFE
R/W
7
–
Refresh Control Register (RCR)
The RCR specifies the interval and length of refresh cycles, while
enabling or disabling the refresh function.
1
0 R/W
R/W
R/W
REFW
R/W
6
1
Value
0
1
0
1
5
Description
REFE: Refresh Enable
Disables the refresh controller
Enables refresh cycle insertion.
Refresh Wait (bit 6)
Causes the refresh cycle to be two clocks in duration.
Causes the refresh cycle to be three clocks in duration by
adding a refresh wait cycle (TRW).
Cycle Interval — CYC1 and CYC0 specify the interval
(in clock cycles) between refresh cycles. In the case of
dynamic RAMs requiring 128 refresh cycles every 2 ms
(or 256 cycles in every 4 ms), the required refresh interval
is less than or equal to 15.625 ms. Thus, the underlined
values indicate the best refresh interval depending on
CPU clock frequency. CYC0 and CYC1 are cleared to 0
during RESET. Refer to Table 11.
4
?
?
?
3
2
CYC1
R/W
1
0
CYC0
R/W
0
0
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