Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 109
![IC 10MHZ Z180 CMOS ENH MPU 64DIP](/photos/6/76/67665/z8018010psg_sml.jpg)
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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94
UM005003-0703
Z8018x
Family MPU User Manual
DMA Destination Address Register Channel 0 (DAR0 I/O Address =
23H to 25H)
Specifies the physical destination address for channel 0 transfers. The
register contains 20 bits and can specify up to 1024KB memory addresses
or up to 64KB I/O addresses. Channel 0 destination can be memory, I/O,
or memory mapped I/O.
DMA Byte Count Register Channel 0 (BCR0 I/O Address = 26H to
27H)
Specifies the number of bytes to be transferred. This register contains 16
bits and may specify up to 64KB transfers. When one byte is transferred,
the register is decremented by one. If n bytes are transferred, n is stored
before the DMA operation.
DMA Memory Address Register Channel 1 (MAR1: I/O Address =
28H to 2AH)
Specifies the physical memory address for channel 1 transfers. This
address may be a destination or source memory address. The register
contains 20 bits and may specify up to 1024KB memory address.
DMA I/O Address Register Channel 1 (IAR1: I/O Address = 2BH to
2CH)
Specifies the I/O address for channel 1 transfers. This address may be a
destination or source I/O address. The register contains 16 bits and may
specify up to 64KB I/O addresses.
DMA Byte Count Register Channel 1 (BCR1: I/O Address = 2EH to
2FH)
Specifies the number of bytes to be transferred. This register contains 16
bits and may specify up to 64KB transfers. When one byte is transferred,
the register is decremented by one.
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