Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 116
![IC 10MHZ Z180 CMOS ENH MPU 64DIP](/photos/6/76/67665/z8018010psg_sml.jpg)
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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DMA/WAIT Control Register (DCNTL: 32H)
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
5
3
1
–
–
–
–
6
4
2
0
MWI1
IWI1
DMS1
DIM1
7
R/W
MWI1
0
–
–
–
0
–
0 R/W
0 R/W
0 R/W
R/W
6
R/W
MWI0
0
Value
5
IWI1
R/W
0
Description
Memory Wait Insertion —Specifies the number of wait
states introduced into CPU or DMAC memory access
cycles. MWI1 and MWI0 are set to 1 during RESET. See
section on Wait State Generator for details.
Wait Insertion — Specifies the number of Wait States
introduced into CPU or DMAC I/O access cycles. IWI1
and IWI0 are set to 1 during RESET. See section on Wait
State Generator for details.
DMA Request Sense — Specifies the DMA request
sense for channel 0 (DREQ0) and channel 1 (
respectively. When reset to 0, the input is level-sense.
When set to 1, the input is edge-sense.
DMA Channel 1 I/O and Memory Mode — Specifies
the source/destination and address modifier for channel 1
memory to/from I/O transfer modes. Reference Table 15.
4
IWI0
R/W
0
3
R/W
DMS1
0
Family MPU User Manual
2
DMS0
R/W
0
1
DIM1
R/W
0
UM005003-0703
Z8018x
DREQ
0
DIM0
R/W
0
1)
101
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