Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 98
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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Interrupt Sources During RESET
Interrupt Vector Register (I)
All bits are reset to
logical address
and internal interrupts) overlap with fixed restart interrupts like RESET
(0), NMI (
vector table(s) are built elsewhere in memory and located on 256 byte
boundaries by reprogramming I with the LD I, A instruction.
IL Register
Bits 7 - 5 are reset to
The IL Register can be programmed to locate the vector table for INT1,
INT2 and internal interrupts on 32-byte subboundaries within the 256
byte area specified by I.
IEF1, IEF2 Flags
Reset to
ITC Register
ITE0 set to 1. ITE1, ITE2 reset to
instruction, which sets IEF1 to
that the ITE1 and ITE2 bits be respectively set to
I/O Control Registers
Interrupt enable bits reset to
CSI/O, ASCI) interrupts are disabled and can be individually enabled by
writing to each I/O control register interrupt enable bit.
0
. Interrupts other than NMI and TRAP are disabled.
0066H
0000H
), INT0 Mode 1 (
0
. Because I =
0
vectored interrupts (INT0 Mode 2, INT1, INT2,
0
. All Z8X180 on-chip I/O (PRT, DMAC,
1
. Enabling INT1 and INT2 also requires
0038H
0
0
. INT0 can be enabled by the EI
locates the vector tables starting at
) and RST (
Family MPU User Manual
1
by writing to ITC.
0000H
UM005003-0703
-
0038H
Z8018x
). The
83
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