Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 88
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
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Note:
1. DMAC operation is suspended by the clearing of the DME (DMA
2. The PC is pushed onto the stack.
3. The contents of IEF1 are copied to IEF2. This saves the interrupt
4. IEF1 is cleared to
5. Execution commences at logical address
The last instruction of an NMI service routine must be RETN (Return
from Non-maskable Interrupt). This restores the stacked PC, allowing the
interrupted program to continue. Furthermore, RETN causes IEF2 to be
copied to IEF1, restoring the interrupt reception state that existed prior to
NMI.
For NMI, take special care to insure that interrupt inputs do not overrun
the NMI service routine. Unlimited NMI inputs without a corresponding
number of RETN instructions eventually cause stack overflow.
Figure 34 depicts the use of NMI and RETN while Figure 35 details NMI
response timing. NMI is edge sensitive and the internally latched NMI
falling edge is held until it is sampled. If the falling edge of NMI is
latched before the falling edge of the clock state prior to T3 or T1 in the
last machine cycle, the internally latched NMI is sampled at the falling
edge of the clock state prior to T3 or T1 in the last machine cycle and
NMI acknowledge cycle begins at the end of the current machine cycle.
Main Enable) bit in DCNTL.
reception state that existed prior to NMI.
interrupts (that is, all interrupts except NMI and TRAP).
DMAC operation, can be used to externally interrupt DMA
transfer. The NMI service routine can reactivate or abort the
DMAC operation as required by the application.
NMI, because it can be accepted during Z8X180 on-chip
0
. This disables all external and internal maskable
Family MPU User Manual
0066H
.
UM005003-0703
Z8018x
73
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