Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 96
![IC 10MHZ Z180 CMOS ENH MPU 64DIP](/photos/6/76/67665/z8018010psg_sml.jpg)
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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also the interrupt response sequence used for all internal interrupts
(except TRAP).
As depicted in Figure 41, the low-order byte of the vector table address
has the most significant three bits of the software programmable IL
register while the least significant five bits are a unique fixed value for
each interrupt (INT1, INT2 and internal) source:
Figure 41.
INT1 and INT2 are globally masked by IEF1 is
individually maskable by respectively clearing the ITE1 and ITE2 (bits
1,2) of the INT/TRAP control register to
During RESET, IEF1, ITE1 and ITE2 bits are reset to
Internal Interrupts
Internal interrupts (except TRAP) use the same vectored response mode
as INT1 and INT2. Internal interrupts are globally masked by IEF1 is
Individual internal interrupts are enabled/disabled by programming each
I
16-bit Vector
INT1, INT2 Vector Acquisition
IL
Fixed Code
(5 bits)
Vector + 1
Vector
of starting address
of starting address
Low-order 8 bits
High-order 8 bits
0
Family MPU User Manual
.
Memory
0
. Each is also
0
.
UM005003-0703
32 Bytes
Vector
Table
Z8018x
0
.
81
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