Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 72
![IC 10MHZ Z180 CMOS ENH MPU 64DIP](/photos/6/76/67665/z8018010psg_sml.jpg)
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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Whether address translation (Figure 26) takes place depends on the type
of CPU cycle as follows.
•
•
Figure 26.
•
MMU Registers
Three MMU registers are used to program a specific configuration of
logical and physical memory.
Memory Cycles
Address Translation occurs for all memory access cycles including
instruction and operand fetches, memory data reads and writes,
hardware interrupt vector fetch, and software interrupt restarts.
I/O Cycles
The MMU is logically bypassed for I/O cycles. The 16-bit logical I/O
address space corresponds directly with the 16-bit physical I/O
address space. The four high-order bits (A16–A19) of the physical
address are always
DMA Cycles
When the Z8X180 on-chip DMAC is using the external bus, the
MMU is physically bypassed. The 20-bit source and destination
registers in the DMAC are directly output on the physical address bus
(A0–A19).
“0000”
PA19
I/O Address Translation
PA16 PA15
0
during I/O cycles.
LA15
Family MPU User Manual
LA0
PA0
UM005003-0703
Logical Address
Physical Address
Z8018x
57
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