Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 34
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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The Op Code on the data bus is latched at the rising edge of T3 and the
bus cycle terminates at the end of T3.
Figure 9.
Figure 10 illustrates the insertion of Wait States (TW) into the Op Code
fetch cycle. Wait States (TW) are controlled by the external WAIT input
combined with an on-chip programmable Wait State generator.
At the falling edge of T2 the combined WAIT input is sampled. If WAIT
input is asserted Low, a Wait State (TW) is inserted. The address bus,
MREQ, RD and M1 are held stable during Wait States. When WAIT is
sampled inactive High at the falling edge of TW, the bus cycle enters T3
and completes at the end of T3.
A0
D0
MREQ
WAIT
–
–
A19
Phi
RD
M1
D7
Op Code Fetch (without Wait State) Timing Diagram
T1
T2
T3
Family MPU User Manual
T1
T2
UM005003-0703
Z8018x
19
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