Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 309

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

I/O Registers
INTERNAL I/O REGISTERS
Register
ASCI Control Register A
Channel 0:
ASCI Control Register A
Channel 1:
By programming IOA7 and IOA6 as the I/O control register, internal I/O
register addresses are relocatable within ranges from
the I/O address space.
Table 57.
CNTLA0
CNTLA1
Mnemonics Address
Internal I/O Registers
0
0
0
1
during RESET
during RESET
MOD 2 1 0
R/W
R/W
bit
bit
0 0 0 Start + 7 bit Data + 1 Stop
0 0 1 Start + 7 bit Data + 2 Stop
0 1 0 Start + 7 bit Data + Parity + 1 Stop
0 1 1 Start + 7 bit Data + Parity + 2 Stop
1 0 0 Start + 8 bit Data + 1 Stop
1 0 1 Start + 8 bit Data + 2 Stop
1 1 0 Start + 8 bit Data + Parity + 1 Stop
1 1 1 Start + 8 bit Data + Parity + 2 Stop
MPE
R/W
MPE
R/W
0
0
Multi Processor Enable
Multi Processor Enable
R/W
Family MPU User Manual
RE
0
R/W
RE
0
Receive Enable
Receive Enable
R/W
TE
Remarks
R/W
0
TE
0
Transmit Enable
Transmit Enable
RTS0
R/W
CKA1D
R/W
1
1
Request to Send
0000H
CKA1 Disable
MPBR/
invalid
EFR
R/W
invalid
MPBR/
EFR
R/W
Multi Processor Bit Receive/
Error Flag Reset
UM005003-0703
Multi Processor Bit Receive/
Error Flag Reset
MOD2 MOD1
R/W
MOD2 MOD1
R/W
1
0
to
0
Z8018x
00FFH
R/W
R/W
0
0
MODE Selection
MODE Selection
MOD0
R/W
MOD0
R/W
0
0
in
293