Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 56

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

STANDBY-QUICK RECOVERY Mode
Internal I/O Registers
Note:
except that the 2
asserted eight clock cycles after the exit conditions are gathered.
STANDBY-QUICK RECOVERY mode is an option offered in
STANDBY mode to reduce the clock recovery time in STANDBY mode
from 2
MHz). This feature can only be used when providing an oscillator as
clock source.
To enter STANDBY-QUICK RECOVERY mode:
1. Set bits 6 and 3 to
2. Set the I/O STOP bit (bit 5 of ICR, I/O Address =
3. Execute the SLEEP instruction
When the part is in STANDBY-QUICK RECOVERY mode, the operation
is identical to STANDBY mode except when exit conditions are gathered,
using RESET, BUS REQUEST or EXTERNAL INTERRUPTS. The
clock and other control signals are recovered sooner than the STANDBY
mode.
The Z8X180 internal I/O Registers occupy 64 I/O addresses (including
reserved addresses). These registers access the internal I/O modules
(ASCI, CSI/O, PRT) and control functions (DMAC, DRAM refresh,
interrupts, wait state generator, MMU and I/O relocation).
17
If STANDBY-QUICK RECOVERY is enabled, the user must
ensure stable oscillation is obtained within 64 clock cycles
clock cycles (4 ms at 33 MHz) to 2
17
bit wake-up timer is bypassed. All control signals are
1
and
1
, respectively.
Family MPU User Manual
6
clock cycles (1.9 ms at 33
3FH
UM005003-0703
) to
Z8018x
1
.
41